ROR shifts the bits of the destination to the right by the number of bit positions specified in the count operand. As bits are transferred out the right (low-order) end of the destination, they re-enter on the left (high-order) end. The carry flag (CF) is updated to match the last bit shifted out of the right end.
The shift is repeated the number of times indicated by the second operand, which is either an immediate 8-bit value (max. 1 on the 8086 processor) or the contents of the CL register. To reduce the maximum execution time, the 80186+ uses only the lower 5 bits of the count, limiting the count value to 31; the 8086 uses all 8 bits of count.
If the count operand is not an immediate 1, the overflow flag (OF) is undefined; otherwise ROR sets OF to 0 if destination's sign bit was not changed by the operation, to 1 if the sign bit was changed.