RCR             Rotate through Carry Right           Flags: O D I T S Z A P C
* - - - - - - - *
RCR destination,count

┌─────────────────────◄───┐
│ ┌───────────────┐ ┌──┴─┐
└─►│ destination │──►│ CF │
└───────────────┛ └────┛

RCR shifts the bits of the destination operand to the right by the
number of bit positions specified in the count operand. A bit
shifted out of the right (low-order) end of the destination enters
the carry flag (CF), and the displaced carry flag rotates around
to enter the vacated left-most bit position of the destination.
Another way of looking at this is to consider the carry flag as
the lowest order bit of the word being rotated.

The shift is repeated the number of times indicated by the second
operand, which is either an immediate 8-bit value (max. 1 on the
8086 processor) or the contents of the CL register. To reduce the
maximum execution time, the 80186+ uses only the lower 5 bits of
the count, limiting the count value to 31; the 8086 uses all 8
bits of count.

If the count operand is not an immediate 1, the overflow flag (OF)
is undefined; otherwise RCR sets OF to 0 if destination's sign bit
was not changed by the operation, to 1 if the sign bit was changed.


Opcode Format
C0 /3 ib RCR r/m8,imm8
C1 /3 ib RCR r/m16,imm8
C1 /3 ib RCR r/m32,imm8
D0 /3 RCR r/m8,1
D1 /3 RCR r/m16,1
D1 /3 RCR r/m32,1
D2 /3 RCR r/m8,CL
D3 /3 RCR r/m16,CL
D3 /3 RCR r/m32,CL


Length and timing
Operands Bytes 8088 186 286 386 486 Pentium
reg, 1 2 2 2 2 9 3 1 PU
mem, 1 2+d(0,2) 23+EA 15 7 10 4 3 PU
reg, cl 2 8+4n 5+n 5+n 9 8-30 7-24 NP
mem, cl 2+d(0,2) 28+EA+4n 17+n 8+n 10 9-31 9-26 NP
reg, imm 3 - 5+n 5+n 9 8-30 8-25 NP
mem, imm 3+d(0,2) - 17+n 8+n 10 9-31 10-27 NP