Flags register
The EFLAGS register controls I/O, maskable interrupts, debugging,
task switching, and enabling of virtual 8086 execution in a
protected, multitasking environment; all in addition to providing
status flags that represent the result of instruction execution.
The low 16 bits (0-15) of EFLAGS contain the FLAGS register (8086-
80286).
3 2 1
1 3 5 7 0
┌─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┬─┐
│ │I│V│V│A│V│R│ │N│IO │O│D│I│T│S│Z│ │A│ │P│ │C│
│r r r r r r r r r r│D│I│I│C│M│F│r│T│ PL│F│F│F│F│F│F│r│F│r│F│r│F│
└─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴P┴F┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┛
r = reserved by Intel
Carry CF is set if the operation resulted in a carry
out of the high-order bit (an addition), or a
borrow into the high-order bit (a subtraction).
Otherwise, CF is reset to zero. For 8-, 16-,
or 32-bit operations, CF is set according to
the carry/borrow at bit 7, 15, or 31.
Parity PF is set if the low-order eight bits of the
operation contains an even number of "1's"
(even parity). PF is reset to zero if the
low-order eight bits have odd parity. PF is
always a function of only the low-order eight
bits, regardless of operand size.
Often used by communications programs.
Adjust AF (sometimes called the auxilliary carry or the
BCD carry) simplifies the addition and
subtraction of packed BCD quantities. Regardless
of the operand size (8, 16, or 32 bits), AF is
set if the operation resulted in a borrow into
bit 3 (which is a subtraction) or a carry out of
bit 3 (which is an addition). BCD uses bits 0
thru 3 to represent decimal digits.
Zero ZF is set if all bits of the result are zero.
Otherwise, it is reset.
Sign SF is set if the high-order bit of the result
is set. It is reset otherwise. For 8-, 16, and
32-bit operations, SF reflects the state of
bit 7, 15, and 31, respectively.
Trap Setting TF puts the processor into single-step
mode for debugging. The CPU automatically
generates an Exception 1 after each
instruction, which allows a program to be
inspected as it executes each instruction.
When TF is reset, exception 1 traps occur only
as a function of the breakpoint addresses
loaded into the debug registers DR0-DR3.
Interrupt Setting IF allows the CPU to recognize
external (maskable) interrupt requests.
Clearing this bit disables these interrupts.
IF has no effect on either non-maskable
external interrupts or exceptions.
Direction DF defines whether the (E)SI and/or (E)DI
registers are to increment or decrement during
string operations (LODS, STOS, MOVS, CMPS,
SCAS, INS, OUTS). If DF=0, the registers
increment, if DF=1, they decrement.
Overflow OF is set if the operation resulted in
carry/borrow into the sign bit (high-order
bit) of the result but did not result in a
carry/borrow out of the high-order bit, or
vice-versa.
Occurs when the size of a computation exceeds
the size of the destination.
IOPL (80286+) This two-bit field applies to
protected mode. Input/Output Privilege Level
(IOPL) shows the highest current privilege
level (CPL) value permitted to execute I/O
instructions without generating an exception
13 fault or consulting the I/O Permission
Bitmap. It also shows the highest CPL value
that allows change of the IF (INTR Enable
Flag) when new values are popped into the
EFLAGS register (see POPF).
Nested task (80286+) The CPU uses this flag to control
chaining of interrupted and CALLed tasks. A
CALL transfers the program execution sequence
on a temporary basis to a subroutine or
subprogram. On termination of that subroutine,
execution is resumed at the instruction
following the CALL. NT influences the
operation of the IRET instruction.
Resume (80386+) This flag temporarily disables debug
exceptions (breaks to normal program flow) so
that an instruction can be restarted after a
debug exception without immediately causing
another one.
Virtual 8086 mode (80386+) The VM bit provides Virtual 8086
Mode within the protected mode. If set while
the processor is in protected mode, the CPU
switches to Virtual 8086 operation. The VM bit
can be set only in two ways: in protected
mode by the IRET instruction and only if
Current Privilege Level is zero, and by task
switches at any privilege level.
Alignment check (80486+) Setting AC lets the 80486+ check the
alignment of operands when you make references
to memory. The processor issues an alignment-
check exception when a reference is made to an
unaligned operand, such as a word that starts
on an odd-numbered address or a doubleword
that starts at an address that is not a
multiple of four. Alignment-check exceptions
are generated only in user mode (privilege
level 3).
ID capability (Pentium+, later 80486s) Indicates whether the
processor is capable of executing the CPUID
instruction.
VIF (Pentium+) Virtual Interrupt Flag, bit 19.
Virtual image of the IF flag. Used in
conjunction with the VIP flag. (To use VIF and
VIP, the CR4.VME bit must be set.)
VIP (Pentium+) Virtual Interrupt Pending, bit 20.
Set to indicate that an interrupt is pending;
clear when no interrupts are pending. (Software
sets and clears this flag. The processor only
reads it.) Used in conjunction with the VIF
flag.
Note: The flags register is referred to as 'Status word' on the
80186 processor.