XCHG            Exchange Registers                   Flags: Not altered

XCHG destination,source

        Logic   destination ←→ source

    XCHG switches the contents of two operands.

    If a memory operand is involved, BUS LOCK is asserted for the
    duration of the exchange, regardless of the presence or absence of
    the LOCK prefix or the value of the IOPL.


    Opcode      Format
    86 /r       XCHG r/m8,r8
    86 /r       XCHG r8,r/m8
    87 /r       XCHG r/m16,r16
    87 /r       XCHG r16,r/m16
    87 /r       XCHG r/m32,r32
    87 /r       XCHG r32,r/m32
    90 + rw     XCHG AX,r16
    90 + rw     XCHG r16,AX
    90 + rd     XCHG EAX,r32
    90 + rd     XCHG r32,EAX


    Length and timing
    Operands    Bytes   8088    186     286     386     486     Pentium
    reg, reg     2       4       4       3       3       3       3   NP
    reg, mem   2+d(0-2)  25+EA  17       5       5       5       3   NP
    mem, reg   2+d(0-2)  25+EA  17       5       5       5       3   NP
    acc, reg     1       3       3       3       3       3       2   NP
    reg, acc     1       3       3       3       3       3       2   NP

    (acc = AX or EAX only)