Loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. If less than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.
The MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors. Appendix C, Model-Specific Registers (MSRs), in the Pentium Pro Family Developer's Manual, Volume 3 lists all the MSRs that can be read with this instruction and their addresses. The CPUID instruction should be used to determine whether MSRs are supported (EDX[5]=1) before using this instruction.
Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If the value in ECX specifies a reserved or unimplemented MSR address.
Real Address Mode Exceptions #GP If the current privilege level is not 0 If the value in ECX specifies a reserved or unimplemented MSR address.
Virtual 8086 Mode Exceptions #GP(0) The RDMSR instruction is not recognized in virtual 8086 mode.