The 80386+ registers are a superset of 8086/80186/80286 registers.
    All the previous generations' 16-bit registers are contained
    within the 32-bit architechture.

Register availability
                          Use in    │     Use in     │   Use in
                         REAL mode  │ PROTECTED mode │  V86 mode
                        Load  Store │  Load  Store   │ Load  Store
                        ────────────┼────────────────┼────────────
    General registers   yes    yes  │  yes    yes    │ yes    yes
    Segment registers   yes    yes  │  yes    yes    │ yes    yes
    Flags register      yes    yes  │  yes    yes    │ IOPL   IOPL
    GDT register        yes    yes  │  CPL=0  yes    │ no     yes
    LDT register        no     no   │  CPL=0  yes    │ no     yes
    IDT register        yes    yes  │  CPL=0  yes    │ no     yes
    Task register       no     no   │  CPL=0  yes    │ no     yes
    Control registers   yes    yes  │  CPL=0  CPL=0  │ no     no
    Debug registers     yes    yes  │  CPL=0  CPL=0  │ no     no
    Test registers      yes    yes  │  CPL=0  CPL=0  │ no     no

    CPL=0 : The register can be accessed only when the current
            privilege level (CPL) is zero.
    IOPL  : The PUSHF and POPF instructions are made I/O Privilege
            Level sensitive in virtual 8086 mode. CPL=3 in V86 mode.
    Note  : The low-order 16 bits of control register zero (CR0) can
            be read with an SMSW instruction.
            The CLI and STI instructions are IOPL-sensitive in
            protected mode, incl. V86 mode.
            Test registers 80386-80486 only.