Control registers


     3               2         1   1         1
     1               3         8   6         1           5 4 3 2 1 0
    ┌───────────────────────────────────────┬─────────────┬─┬─┬─┬─┬─┐
    │ Page directory base register (PDBR)   │ Reserved    │P│P│0 0 0│ CR3
    │                                       │             │C│W│     │
    ├───────────────────────────────────────┴─────────────┴─┴─┴─┴─┴─┤
    │                  Page fault linear address                    │ CR2
    │                                                               │
    ├───────────────────────────────────────────────────────────────┤
    │                          Reserved                             │ CR1
    │                                                               │
    ├─┬─┬─┬───────────────────┬─┬─┬─┬───────────────────┬─┬─┬─┬─┬─┬─┤
    │P│C│N│ Reserved          │A│ │W│ Reserved          │N│E│T│E│M│P│ CR0
    │G│D│W│                   │M│ │P│                   │E│T│S│M│P│E│
    └─┴─┴─┴───────────────────┴─┴─┴─┴───────────────────┴─┴─┴─┴─┴─┴─┛
     7 6 5 4 3 2 1 0                 7 6 5 4 3 2 1 0
                     7 6 5 4 3 2 1 0                 7 6 5 4 3 2 1 0

    CR0 - Control Register 0

    The low 16 bits of CR0 contain the MSW register (80286 machine
    status word).

    PG bit 31           PG (paging) indicates whether the 80486 uses
                        page tables to translate linear addresses into
                        physical addresses.         (80386+)
    CD bit 30           CD (1 = cache disabled)     (80486+)
    NW bit 29           NW (0 = not write-through)  (80486+)
    AM bit 18           AM (alignment mask) enables (when set) or
                        disables (when clear) checking the alignment
                        of memory operands.         (80486+)
    WP bit 16           WP (write-protect)          (80486+)
                        (1 if read-only pages protected)
    NE bit  5           NE (numeric error)          (80486+)
                        (1 if errors should be ignored)
    ET bit  4           ET (extension type)         (80386+)
                        (1= 80387,0=80287 type)
    TS bit  3           TS (1 = task switched)      (80286+)
    EM bit  2           EM (emulation)              (80286+)
                        (1= execute exception 7 on FPU codes)
    MP bit  1           MP (math present)           (80286+)
                        (1 if FPU handles FPU codes)
    PE bit  0           Setting PE (protection enable) causes the
                        processor to begin executing in protected
                        mode. Resetting PE returns to real-address
                        mode.                       (80286+)


    CR1 - Control Register 1

    Reserved for future Intel processors.


    CR2 - Control Register 2

    Used for handling exceptions generated during paging, or page
    faults, when the PG flag in CR0 is set.


    CR3 - Control Register 3

    Used when the PG flag in CR0 is set. CR3 contains the physical
    base address of the page directory table for the current task. The
    page directory must be aligned to a page (4 KB-aligned), so the
    low 12 bits of CR3 are ignored.

    PCD bit 4           PCD (page-level cache disable)  (80486+)
    PWT bit 3           PWT (page-level write through)  (80486+)


    CR4 - Control Register 4  (Pentium and PPro)

    Extended Machine Control
    Bit
     0  VME  Virtual86 mode Virtual Interrupts (1=use VIF flag in VM)
     1  PVI  Protected mode Virtual Interrupts (1=use VIF flag in PM)
     2  TSD  Time Stamp instruction Disable (1=RDTSC only with CPL=0)
     3  DE   Debugging Extension (1=breakpoints also valid for I/O)
     4  PSE  Page Size Extension (1=4 Mb paging instead of 4 Kb)
     5  PAE  Physical Address Extension                 (PPro)
     6  MCE  Machine Check Enable (1=enabled)
     7  PGE  Page Global Enable                         (PPro)
     8  PCE  Performance counters enable                (PPro)
    9-31 Reserved