Int 1A Fn B10A - Pci Bios V2.0c+ - Read Configuration Dword (intel Devices) (Cont.)
5 shutdown to port 92h (82439HX)
=1 send 01h to PORT 0092h on Shutdown special cycle on host bus
4 dual-processor NA# enable (82439HX)
3 PCI Concurrency Enable
=1 CPU can access DRAM/L2 during non-PIIX PCI master cycles
=0 CPU kept off PCI bus during all PCI bus-master cycles
2 SERR# Output Type (82439HX only)
=1 SERR# is actively driven high when negated
=0 SERR# is PCI-compatible open-drain output
1 reserved
0 Global TXC Enable (82439HX only)
=1 enable new 82439HX features
See Also: #0892,#0888,#0896,#0895
Bitfields for Intel 82437FX/82437MX PCI Control register:
Bit(s) Description (Table 0895)
7-5 CPU inactivity timer (in PCI Clocks less 1)
4 reserved
3 enable PCI Peer Concurrency
=1 CPU can access DRAM/L2 during non-PIIX PCI master cycles
=0 CPU kept off PCI bus during all PCI bus-master cycles
2 disable PCI Bursting
1 disable PCI Streaming
0 disable Bus Concurrency
See Also: #0890,#0891,#0894
Bitfields for Intel 82437/82439HX cache control register:
Bit(s) Description (Table 0896)
7-6 secondary cache size
00 none
01 256K
10 512K
11 reserved
5-4 L2 RAM type
00 pipelined burst SRAM/DRAM
01 reserved
10 asynchronous SRAM (82437FX/MX/VX only)
11 two banks of pipelined burst cache
3 NA disable
=1 never assert NA# pin
2 reserved (82437FX/82437MX/82437VX)
2 Extended Cacheability Enable (82439HX)
=1 cache up to 512M
=0 cache only first 64M
1 Secondary Cache Force Miss or Invalidate
=1 force all memory accesses to bypass L2 cache
0 First Level Cache Enable
=1 all memory accesses made non-cacheable by CPU L1 cache
See Also: #0892,#0888,#0894,#0897,#0898,#0890
Bitfields for Intel 82437VX cache control extensions register:
Bit(s) Description (Table 0897)
7-6 reserved
5 DRAM cache detected (read-only)
4-0 DRAM cache refresh timer
number of HCLKs 82437VX remains idle during DRAM cache refresh
See Also: #0892,#0896
Bitfields for Intel 82437VX SDRAM control register:
Bit(s) Description (Table 0898)
15-9 reserved
8-6 Special SDRAM Mode Select
000 normal mode (default)
001 enable NOP command
010 enable All Banks Precharge command
011 enable Mode Register Command
100 enable CBR Cycle
101 reserved
11x reserved
5 reserved
4 CAS# latency
=1 latency is 2 for all SDRAM cycles
=0 latency is 3
3 RAS# precharge and refresh timing
=0 slower
=1 faster
2-0 reserved
See Also: #0892,#0896
Bitfields for Intel 82437VX/82439HX DRAM extended control register:
Bit(s) Description (Table 0899)
7 reserved
6 (82437VX) refresh RAS# assertion length (0=4 clocks, 1=5 clocks)
5 (82437VX) Fast EDO Path Select
4 Speculative Leadoff Disable
3 (82439HX) Turn-Around Insertion Enable
=1 insert one extra clock of turnaround time after asserting MWE#
2-1 Memory Address Drive Strength
82437VX: 82439HX:
00 reserved 00 8mA
01 10mA (default) 01 8mA/12mA (MAA/MWE#)
10 16mA 10 12mA/8mA (MAA/MWE#)
11 reserved 11 12mA
0 (82437VX) DRAM Symmetry Detect Mode
(used to force some memory address lines to fixed value for detecting
DRAM symmetry row-by-row)
0 (82439HX) 64MBit Mode Enable
=1 enable support for 64M SIMMs
See Also: #0892,#0888,#0900
Bitfields for Intel 82437/82439HX DRAM control register:
Bit(s) Description (Table 0900)
7-6 DRAM Hole Enable
00 none
01 512K-640K
10 15M-16M (82437FX/MX/VX only)
11 14M-16M (82437VX only)
5 reserved
4 (82437MX only) refresh type during Suspend
=1 self-refreshing DRAMs in system
=0 CAS-before-RAS refresh
3 EDO Detect Mode enable
(used to detect whether memory is EDO bank-by-bank)
2-0 DRAM refresh rate
FX/VX/HX MX
000 disabled 15.6 us
001 50 MHz 31.2 us
010 60 MHz 62.4 us
011 66 MHz 125 us
100 reserved 250 us
1xx reserved reserved
See Also: #0892,#0888,#0899,#0890
Bitfields for Intel 82437FX/82437MX/82437VX/82439HX DRAM timing register:
Bit(s) Description (Table 0901)
7 (82437FX) reserved
7 (82437MX) MA[11:2] buffer strength
=0 8mA
=1 12mA
7 (82437VX) MA-to-RAS# Delay
=1 one clock
=0 two clocks
7 (82439HX) Turbo Read Leadoff
=1 bypass first register in DRAM data pipeline, saving one clock
(may only be set in a cacheless configuration)
6-5 DRAM Read Burst Timing
00 x444 (EDO and Standard Page Mode)
01 x333 (EDO), x444 (SPM)
10 x222 (EDO), x333 (SPM)
11 x322 (EDO), x333 (SPM) (82437VX only)
11 reserved (other)
4-3 DRAM Write Burst Timing
00 x444
01 x333
10 x222
11 reserved
2 RAS-to-CAS Delay
=1 two clocks
=0 three clocks
1-0 DRAM Leadoff Timing
82437VX Read Leadoff Write Leadoff RAS# Precharge
00 11 7 3
01 10 6 3
10 11 7 4
11 10 6 4
82437FX/MX Read Lead Write Leadoff RAS# Precharge
00 8 6 3
01 7 5 3
10 8 6 4
11 7 5 4
82437VX Read Leadoff Write Leadoff RAS# Precharge
00 7 6 3
01 6 5 3
10 7 6 4
11 6 5 4
See Also: #0892,#0900,#0890,#0891
Bitfields for Intel 82434/82437/82439HX Programmable Attribute Map Register:
Bit(s) Description (Table 0902)
7 reserved
6 cache enable (region 1)
5 write enable (region 1)
4 read enable (region 1)
3 reserved
2 cache enable (region 0)
1 write enable (region 0)
0 read enable (region 0)
Notes: each programmable attribute map register controls two memory
regions at the top of the first megabyte of memory
for the Intel 82441FX, bits 6 and 2 are reserved, as cacheability is
set using the Pentium Pro's MTRR registers (see MSR 000000FEh)
Intel 82434/82437FX/82437MX/82437VX/82439HX/82441FX PAM
registers/regions:
PAM0 low: reserved [*]
PAM0 hi: segment F000-FFFF
PAM1 low: segment C000-C3FF
PAM1 hi: segment C400-C7FF
PAM2 low: segment C800-CBFF
PAM2 hi: segment CC00-CFFF
PAM3 low: segment D000-D3FF
PAM3 hi: segment D400-D7FF
PAM4 low: segment D800-DBFF
PAM4 hi: segment DC00-DFFF
PAM5 low: segment E000-E3FF
PAM5 hi: segment E400-E7FF
PAM6 low: segment E800-EBFF
PAM6 hi: segment EC00-EFFF
[*] on the 82434 (and possibly other Intel chipsets), the low nybble of
PAM0 controls segment 8000-9FFF
See Also: #0851,#0892,#0888,#0927,#0890,#0891
Bitfields for Intel 82437VX DRAM Row Type register:
Bit(s) Description (Table 0903)
7,3 row 3 type
6,2 row 2 type
5,1 row 1 type
4,0 row 0 type
00 SPM DRAM
01 EDO DRAM
10 SDRAM
11 reserved
See Also: #0892,#0902
Bitfields for Intel 82437FX/82437MX DRAM Row Type register:
Bit(s) Description (Table 0904)
7-4 reserved
3-0 DRAM Row N is EDO instead of page-mode DRAM
See Also: #0890,#0891
Bitfields for Intel 82437VX PCI TRDY timer:
Bit(s) Description (Table 0905)
7-3 reserved
2-0 TRDY timeout value
000 2 PCICLKs
001 4 PCICLKs
010 6 PCICLKs
011 8 PCICLKs
1xx reserved
See Also: #0892,#0906
Bitfields for Intel 82437/82439HX System Management RAM control register:
Bit(s) Description (Table 0906)
7 reserved
6 SMM Space Open
=1 make SMM DRAM visible even when not in SMM if bit 4 =0
5 SMM Space Closed
=1 no data references permitted to SMM DRAM even in SMM
4 SMM Space Locked
=1 force bits 4 and 6 to become read-only; and clear bit 6
3 SMRAM Enable
=1 128K DRAM are accessible for use at A000 while in SMM
2-0 SMM Space Base Segment
010 segment A000-BFFF
100 segment C000-CFFF (82437MX only)
other reserved
Note: bits 5 and 6 must never both be set at the same time
See Also: #0892,#0888,#0907,#0890,#0891
Bitfields for Intel 82437VX Shared Memory Buffer control register:
Bit(s) Description (Table 0907)
7-2 reserved
1 enable shared memory buffer
0 redirect shared memory buffer access
=0 treat SMB area as a hole in system DRAM
See Also: #0892,#0906,#0908
Bitfields for Intel 82437VX Graphics Controller Latency Timer:
Bit(s) Description (Table 0908)
7-6 reserved
5-3 GC latency for PCI reads (in 4 HCLK multiples) (default=100)
2-0 GC latency for CPU and PCI writes (in 4 HCLK multiples) (default=011)
See Also: #0892,#0907
Bitfields for Intel 82439HX Error Command register:
Bit(s) Description (Table 0909)
7 SERR# duration
=0 one PCI clock
=1 until error flags are cleared
6-3 reserved
2 force bad parity on multiple-bit uncorrectable error
1 assert SERR# on multiple-bit uncorrectable error
0 assert SERR# on single-bit correctable error
See Also: #0888,#0910
Bitfields for Intel 82439HX Error Status register:
Bit(s) Description (Table 0910)
7-5 DRAM row associated with multi-bit error
4 multi-bit uncorrectable error occurred (write 1 bit to clear)
3-1 DRAM row associated with single-bit correctable error
0 single-bit correctable error occurred (write 1 bit to clear)
See Also: #0888,#0909
Format of PCI Configuration for Intel 82371FB/82371SB Function 0 (ISA Bridge):
Offset Size Description (Table 0911)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 122Eh/7000h)
(revision ID 00h = 82371SB step A-1)
(revision ID 01h = 82371SB step B-0)
40h 12 BYTEs reserved
4Ch BYTE ISA I/O Controller Recovery Timer (see #0883)
4Dh BYTE reserved
4Eh BYTE X-Bus Chip Select Enable (see #0885)
4Fh BYTE (82371SB) X-Bus Chip Select Enable High
bit 0: I/O APIC enabled
4Fh BYTE (82371FB) reserved
50h 16 BYTEs reserved
60h 4 BYTEs PCI IRQ Route Control (see #0872)
64h 5 BYTEs reserved
69h BYTE top of memory (see #0914)
6Ah WORD miscellaneous status (see #0915)
6Ch 4 BYTEs reserved
70h BYTE motherboard IRQ Route Control 0 (see #0916)
71h BYTE (82371FB) motherboard IRQ Route Control 1 (see #0916)
72h 4 BYTEs reserved
76h 2 BYTEs motherboard DMA control (see #0917)
78h WORD programmable chip select control (see #0918)
7Ah 6 BYTEs reserved
80h BYTE (82371SB) APIC Base Address Relocation (see #0874)
81h BYTE reserved
82h BYTE (82371SB) Deterministic Latency Control (see #0919)
83h 29 BYTEs reserved
A0h BYTE SMI Control (see #0920)
A1h BYTE reserved
A2h WORD SMI Enable (see #0876)
A4h DWORD System Event Enable (SEE) (see #0877)
A8h BYTE Fast-Off Timer (in minutes, PCICLKs, or milliseconds)
value is count less one; timer must be stopped before
changing its value
A9h BYTE reserved
AAh WORD SMI Request (see #0878)
ACh BYTE Clock Scale STPCLK# Low Timer
STPCLK# stays low for 1+1056*(value+1) PCICLKs
ADh BYTE reserved
AEh BYTE Clock Scale STPCLK# High Timer
STPCLK# stays high for 1+1056*(value+1) PCICLKs
AFh 81 BYTEs reserved
See Also: #0912,#0913,#0860,#0879,#0892,#0888
Format of PCI Configuration for Intel 82371FB/82371SB Function 1 (IDE):
Offset Size Description (Table 0912)
00h 64 BYTEs header (see #0798)
(vender ID 8086h, device ID 1230h/7010h)
20h DWORD Bus Master Interface Base Address
(see PORT xxxxh"Intel 82371SB")
40h WORD IDE timing modes, primary channel (see #0921)
42h WORD IDE timing modes, secondary channel (see #0921)
44h BYTE (82371SB) slave IDE timing register (see #0922)
45h 187 BYTEs reserved
See Also: #0911,#0913,PORT xxxxh"Intel 82371SB"
Format of PCI Configuration data for Intel 82371SB Function 2 (USB):
Offset Size Description (Table 0913)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 7020h)
20h DWORD I/O space base address
(see PORT xxxxh"Intel 82371SB")
40h 32 BYTEs reserved
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