Int 1A Fn B10A - Pci Bios V2.0c+ - Read Configuration Dword (intel Devices) (Cont.)
45h 3 BYTEs ???
48h WORD PCI local-bus IDE control register (see #0882)
4Ah 2 BYTEs ???
4Ch BYTE ISA I/O recovery timer register (see #0883)
4Dh BYTE part revision register (see #0884)
4Eh BYTE X-bus Chip Select A register (see #0885)
4Fh BYTE X-bus Chip Select B register???
50h BYTE host select register
51h BYTE deturbo frequency control register
when deturbo mode is selected (see PORT 0CF9h), the chipset
places a hold on the memory bus for a fraction of the
time inversely proportional to the value in this register
(i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.)
52h WORD secondary (L2) cache control register
54h 2 BYTEs ???
56h WORD DRAM control register
58h BYTE ???
59h 7 BYTEs Programmable Attribute Map (PAM) registers 0-6 (see also #0902)
60h 5 BYTEs DRAM row boundary registers 0-4
each register N indicates amount of memory in rows 0-N (each
row is 64 bits wide); the fifth row of memory (if
implemented) must contain either 8M or 16M, depending on
system configuration
boundary register 4 (offset 64h) contains the total system
memory, which may not exceed 128M
65h BYTE ???
66h BYTE PIRQ route control register 0
67h BYTE PIRQ route control register 1
68h BYTE DRAM memory hole register
69h BYTE top of memory
6Ah 6 BYTEs ???
70h BYTE SMRAM control register
71h 47 BYTEs unused???
A0h BYTE SMI control register
A1h BYTE ???
A2h WORD SMI enable register
A4h DWORD system event enable
A8h BYTE fast off timer register
A9h BYTE ???
AAh WORD SMI request register
ACh BYTE clock throttle STPCLK# low timer
ADh BYTE unused???
AEh BYTE clock throttle STPCLK# high timer
AFh BYTE ???
B0h 80 BYTEs unused???
See Also: #0798,#0859,#0851,#0892,#0911
Bitfields for Intel 82425EX PCI control register:
Bit(s) Description (Table 0880)
0 CPU-to-PCI byte merging
1 CPU-to-PCI bursting enable
2 PCI posted-write buffer enable
4-3 subtractive decode sampling point
00 slow
01 typical
10 fast
11 reserved
5 DRAM parity error enable
6 target abort error enable
7 reserved
See Also: #0879,#0881,#0882,#0883
Bitfields for Intel 82425EX host device control register:
Bit(s) Description (Table 0881)
0 HRDY# maximum signal sampling point
0 slow timing
1 fast timing
1 HDEV# signal sampling point
0 slow timing
1 fast timing
2 host device present
7-3 reserved
See Also: #0879,#0880
Bitfields for Intel 82425EX local-bus IDE control register:
Bit(s) Description (Table 0882)
1-0 primary/secondary PCI IDE enable
00 IDE disabled
01 primary (ports 01F0h-01F7h,03F6,03F7h)
10 secondary (ports 0170h-017Fh,0376h,0377h)
11 reserved
3-2 fast timing bank drive select 1
bit 2 = drive 0 enabled
bit 3 = drive 1 enabled
5-4 IORDY sample point Enable Drive Select
bit 4 = drive 0 enabled
bit 5 = drive 1 enabled
7-6 reserved
9-8 IORDY sample point
00 6 clocks
01 5 clocks
10 4 clocks
11 3 clocks
12-10 recover time (000 = 8 PCI clocks, 001 = 7, ..., 101 = 3, 110/111 = 3)
15-13 reserved
See Also: #0879,#0880
Bitfields for Intel chipset ISA I/O recovery timer register:
Bit(s) Description (Table 0883)
1-0 16-bit I/O recovery time
00 = 4 SYSCLKs
01-11 = 1-3 SYSCLKs
2 16-bit I/O recovery enable
5-3 8-bit I/O recovery time
000 = 8 SYSCLKs
001-110 = 1-7 SYSCLKs
6 8-bit I/O recovery enable
7 (82425EX/82371) DMA reserved page register aliasing disable
=0 ports 0090h-009Fh alias ports 0080h-008Fh
=1 ports 0090h-009Fh forwarded to ISA bus
See Also: #0860,#0879,#0880,#0911
Bitfields for Intel 82425EX part revision register:
Bit(s) Description (Table 0884)
7-5 fabrication house identifier (read-only)
4 E0000h-EFFFFh ISA-to-main-memory forwarding enabled
3-0 revision ID (read-only)
See Also: #0879,#0885
Bitfields for Intel 82425EX/82371 X-bus Chip Select A register:
Bit(s) Description (Table 0885)
7 extended BIOS enabled at FFF80000h-FFFDFFFFh
6 lower (E000h) BIOS enabled
5 trigger IRQ13 on FERR#
4 IRQ12 mouse function enabled
3 reserved (0)
2 BIOS memory write protect
1 keyboard controller addresses (60h,62h,64h,66h) enabled
0 RTC addresses (70h-77h) enabled
See Also: #0879,#0911,#0884
Format of PCI Configuration Data for Intel 82380AB PCI-ISA Bridge:
Offset Size Description (Table 0886)
00h 64 BYTEs header (see #0798)
(vender ID 8086h, device ID 123Ch)
!!!intel\29056301.pdf pg. 9
40h BYTE I/O Recovery Register
41h BYTE reserved
42h BYTE MISA Error Status
43h 189 BYTEs reserved
See Also: #0793
Format of PCI Configuration data for Intel 82370FB PCI-PCI Bridge (MPCI2):
Offset Size Description (Table 0887)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, deivce ID 124Bh)
!!!intel\29056701.pdf pg. 13
40h BYTE Connector Control
41h BYTE Connector Event
42h 2 BYTEs reserved
44h WORD Serial Bus Interface/Burst Enable
46h BYTE MPCI2 Miscellaneous Status
47h 5 BYTEs reserved
4Ch WORD Special Message Encode
4Eh 178 BYTEs reserved
See Also: #0793
Format of PCI Configuration Data for Intel 82439HX:
Offset Size Description (Table 0888)
00h 64 BYTEs header (see #0798)
(vender ID 8086h, device ID 1250h)
(revision ID 00h = A0 stepping)
40h 16 BYTEs reserved
50h BYTE PCI Control (see #0894)
51h BYTE reserved
52h BYTE cache control (see #0896)
53h 3 BYTEs reserved
56h BYTE DRAM extended control (see #0899)
57h BYTE DRAM control (see #0900)
58h BYTE DRAM timing (see #0901)
59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #0902)
60h 8 BYTEs DRAM Row Boundary registers 0-7
each register N indicates cumulative amount of memory in rows
0-N (each 64 bits wide), in 4M units
68h BYTE DRAM Row Type (see #0903)
bits 0-7 indicate whether each row 0-7 contains EDO DRAM
instead of page-mode DRAM
69h BYTE ???
6Ah 8 BYTEs reserved
72h BYTE System Management RAM control (see #0906)
73h 29 BYTEs reserved
90h BYTE Error Command (see #0909)
91h BYTE Error Status (see #0910) (read-only)
92h BYTE Error Syndrome (read-only)
latest non-zero ECC error syndrome
93h 109 BYTEs reserved
See Also: #0892,#0927
Format of PCI Configuration Data for Intel 82439TX:
Offset Size Description (Table 0889)
00h 64 BYTEs header (see #0798)
(vender ID 8086h, device ID 7100h)
(revision ID 00h = A0 stepping)
!!!intel\29055901.pdf pg. 23
40h 15 BYTEs reserved
4Fh BYTE arbitration control
50h BYTE PCI control
51h BYTE reserved
52h BYTE cache control
53h BYTE extended cache control
54h WORD SDRAM control
56h BYTE DRAM extended control
57h BYTE DRAM control
58h BYTE DRAM timing
59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #0902)
60h 6 BYTEs DRAM Row Boundary registers 0-5
66h BYTE reserved
67h BYTE DRAM Row Type high
68h BYTE DRAM Row Type low
69h 2 BYTEs undefined (read-only)
6Bh 5 BYTEs reserved
70h BYTE Multi-Transaction Timer
71h BYTE Extended SMRAM control
72h BYTE System Management RAM control
73h BYTE reserved
74h BYTE undefined (read-only)
76h 3 BYTEs reserved
78h BYTE undefined (read-only)
79h BYTE Miscellaneous Control register
7Ah 131 BYTEs reserved
FDh BYTE undefined (read-only)
FEh 2 BYTEs reserved
See Also: #0793
Format of PCI Configuration Data for Intel 82437MX:
Offset Size Description (Table 0890)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 1235h)
40h 16 BYTEs reserved
50h BYTE PCI Control (see #0895)
51h BYTE reserved
52h BYTE cache control (see #0896)
53h 4 BYTEs reserved
57h BYTE DRAM Control (see #0900)
58h BYTE DRAM timing (see #0901)
59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #0902)
60h 4 BYTEs DRAM Row Boundary Registers 0-3
each register N indicates cumulative amount of memory in rows
0-N, in 4M units (each row is 64 bits wide)
64h 4 BYTEs reserved
68h BYTE DRAM Row Type (see #0904)
69h 9 BYTEs reserved
72h BYTE System Management RAM control (see #0906)
73h 141 BYTEs reserved
See Also: #0892,#0891
Format of PCI Configuration Data for Intel 82437FX:
Offset Size Description (Table 0891)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 122Dh) (see #0793)
40h 16 BYTEs reserved
50h BYTE PCI Control (see #0895)
51h BYTE reserved
52h BYTE cache control (see #0896)
53h 4 BYTEs reserved
57h BYTE DRAM Control (see #0900)
58h BYTE DRAM timing (see #0901)
59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #0902)
60h 5 BYTEs DRAM Row Boundary Registers 0-4
each register N indicates cumulative amount of memory in rows
0-N, in 4M units (each row is 64 bits wide)
65h 3 BYTEs reserved
68h BYTE DRAM Row Type (see #0904)
69h 9 BYTEs reserved
72h BYTE System Management RAM control (see #0906)
73h 141 BYTEs reserved
See Also: #0890,#0892
Format of PCI Configuration Data for Intel 82437VX:
Offset Size Description (Table 0892)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 7030h)
(revision ID 00h = A0 stepping)
40h 15 BYTEs reserved
4Fh BYTE arbitration control (see #0893)
50h BYTE PCI Control (see #0894)
51h BYTE reserved
52h BYTE cache control (see #0896)
53h BYTE cache control extensions (see #0897)
54h WORD SDRAM control (see #0898)
55h BYTE reserved
56h BYTE DRAM extended control (see #0899)
57h BYTE DRAM control (see #0900)
58h BYTE DRAM timing (see #0901)
59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #0902)
60h 5 BYTEs DRAM Row Boundary registers 0-4
each register N indicates amount of memory in rows 0-N in 4M
units (each row is 64 bits wide); the fifth row of memory (if
implemented) must contain either 8M or 16M, depending on
system configuration
boundary register 4 (offset 64h) contains the total system
memory, which may not exceed 128M
65h 2 BYTEs reserved
67h BYTE DRAM Row Type (high)
defines memory type in DRAM row 4 in bits 4,0 (see #0903)
68h BYTE DRAM Row Type (low) (see #0903)
69h BYTE PCI TRDY timer (see #0905)
6Ah 6 BYTEs reserved
70h BYTE Multi-Transaction Timer
number of PCLKs guaranteed to the current agent before the
82437 will grant the bus to another PCI agent on request
71h BYTE reserved
72h BYTE System Management RAM control (see #0906)
73h BYTE shared memory buffer control (see #0907)
74h BYTE shared memory buffer start address, in 0.5MB units
end address is top-of-memory at offset 64h or start of an
enabled PCI memory hole when top-of-memory is 16M
76h 2 BYTEs reserved
78h BYTE graphics controller latency timers (see #0908)
79h 135 BYTEs reserved
See Also: #0793,#0859,#0879,#0888,#0890
Bitfields for Intel 82437VX arbitration control:
Bit(s) Description (Table 0893)
7 extended CPU-to-PIIX PHLDA# signalling enabled
6-4 reserved
3 CPU priority enable
=1 CPU gets PCI bus after two PCI slots
=0 CPU gets PCI bus after three PCI slots
2-0 reserved
See Also: #0892,#0894
Bitfields for Intel 82437VX/82439HX PCI Control register:
Bit(s) Description (Table 0894)
7-4 reserved (82437VX)
7 DRAM ECC/Parity Select (82439HX)
=1 ECC
=0 parity
6 ECC TEST enable (82439HX)
.NG limit reached, continued in next section...