Int 1A Fn B10A - Pci Bios V2.0c+ - Read Configuration Dword (intel Devices) (Cont.)
60h BYTE Serial Bus Specification release number
00h pre-release 1.0
10h Release 1.0
61h 9 BYTEs reserved
6Ah WORD miscellaneous status (see #0923)
6Ch 84 BYTEs reserved
C0h WORD legacy support (see #0924)
C2h 62 BYTEs reserved
See Also: #0911,#0912,PORT xxxxh"Intel 82371SB"
Bitfields for Intel 82371FB/82371SB top of memory register:
Bit(s) Description (Table 0914)
7-4 top of ISA memory (in megabytes, less 1; i.e. 0001 = 2M)
3 ISA/DMA lower BIOS forwarding enable
2 (82371SB) enable A000/B000 segment forwarding to PCI bus
1 enable forwarding ISA/DMA 512K-640K region to PCI bus
0 reserved
See Also: #0911,#0915
Bitfields for Intel 82371FB/82371SB miscellaneous status register:
Bit(s) Description (Table 0915)
15 (82371SB) enable SERR# on delayed transaction
write 1 to clear this bit
14-8 reserved
7 (82371SB) NB Retry Enable
6 (82371SB) EXTSMI# Mode Enable
allow special SERR# protocol between PCI bridge and 82371
5 reserved
4 (82371SB) enable USB
disable USB's master enable and I/O decode enable prior to
clearing this bit!
3 reserved
2 (82371FB) PCI Header Type Bit enable
=1 report multifunction device in PCI configuration header
1 (82371FB) internal ISA DMA/external DMA Mode status (read-only)
=0 normal DMA operation
0 (82371FB) ISA Clock Divisor status (read-only)
(82371SB) ISA Clock Divisor (read-write)
=1 SYSCLK clock divisor is 3
=0 SYSCLK clock divisor is 4
See Also: #0911,#0914
Bitfields for Intel 82371FB/82371SB motherboard IRQ Route Control:
Bit(s) Description (Table 0916)
7 disable IRQ routing
6 enable MIRQx/IRQx sharing
5 (82371SB) enable IRQ0 output
4 reserved (0)
3-0 ISA IRQ number to which to route the PCI IRQ
Note: IRQs 0-2, 8, and 13 are reserved
See Also: #0911,#0914,#0917
Bitfields for Intel 82371FB/82371SB motherboard DMA control:
Bit(s) Description (Table 0917)
7 type F and DMA buffer enable
6-4 reserved
3 (82371FB) disable motherboadr DMA channel
2-0 DMA channel number
(82371FB) Type F and Motherboard DMA
(82371SB) Type F DMA
See Also: #0911,#0916
Bitfields for Intel 82371FB/83271SB programmable chip select control register:
Bit(s) Description (Table 0918)
15-2 I/O address which will assert PCS# signal
1-0 PCS address mask
00 four bytes
01 eight contiguous bytes
10 disabled
11 sixteen contiguous bytes
See Also: #0911,#0917,#0919
Bitfields for Intel 82371SB Deterministic Latency Control register:
Bit(s) Description (Table 0919)
7-4 reserved
3 enable SERR# on delayed transaction timeout
2 enable USB passive release
1 enable passive release
0 enable delayed transactions
See Also: #0911,#0918
Bitfields for Intel 82371FB/82371SB SMI Control Register:
Bit(s) Description (Table 0920)
7-5 reserved
4-3 Fast-Off Timer freeze/granularity selection
00 one minute granularity (assuming 33 MHz PCICLK)
01 disabled (frozen)
10 one PCICLK
11 one millisecond
2 STPCLK# scaling enable
=1 enable Clock Scale bytes in PCI configuration space
1 STPCLK# signal enable
=1 assert STPCLK# on read from PORT 00B2h
0 SMI# Gate
=1 enable SMI# on system management interrupt
Notes: bit 1 is cleared either with an explicit write of 0 here, or by any
write to PORT 00B2h
bit 0 does not affect the recording of SMI events, so a pending SMI
will cause an immediate SMI# when the bit is set
See Also: #0911,#0875
Bitfields for Intel 82371FB/82371SB IDE timing modes:
Bit(s) Description (Table 0921)
15 IDE decode enable
14 (82371SB) slave IDE timing register enable (see #0922)
13-12 IORDY# sample point
00 five clocks after DIOx# assertion
01 four clocks
10 three clocks
11 two clocks
11-10 reserved
9-8 recovery time between IORDY# sample point and DIOx#
00 four clocks
01 three clocks
10 two clocks
11 one clock
7 DMA timing enable only, drive 1
6 prefetch and posting enable, drive 1
5 IORDY# sample point enable drive select 1
4 fast timing bank drive select 1
3 DMA timing enable only, drive 0
2 prefetch and posting enable, drive 0
1 IORDY# sample point enable drive select 0
0 fast timing bank drive select 0
See Also: #0912
Bitfields for Intel 82371SB slave IDE timing register:
Bit(s) Description (Table 0922)
7-6 secondary drive 1 IORDY# sample point
00 five clocks after DIOx# assertion
01 four clocks
10 three clocks
11 two clocks
5-4 secondary drive 1 recovery time
00 four clocks
01 three clocks
10 two clocks
11 one clock
3-2 primary drive 1 IORDY# sample point
1-0 primary drive 1 recovery time
See Also: #0921
Bitfields for Intel 82371SB miscellaneous status:
Bit(s) Description (Table 0923)
15-1 reserved
0 USB clock selection
=1 48 MHz
=0 24 MHz
See Also: #0913,#0924
Bitfields for Intel 82371SB legacy support register:
Bit(s) Description (Table 0924)
15 A20GATE pass-through sequence ended
write 1 to clear this bit
14 reserved
13 USB PIRQ enabled
12 USR IRQ status (read-only)
11 trap caused by write to PORT 0064h
write 1 to clear this bit
10 trap caused by read from PORT 0064h
write 1 to clear this bit
9 trap caused by write to PORT 0060h
write 1 to clear this bit
8 trap caused by read from PORT 0060h
write 1 to clear this bit
7 enable SMI at end of A20GATE Pass-Through
6 A20GATE pass-through sequence in progress (read-only)
5 enable A20GATE pass-through sequence
(write PORT 64h,D1h; write 60h,xxh; read 64h; write 64h,FFh)
4 enable trap/SMI on USB IRQ
3 enable trap/SMI on PORT 0064h write
2 enable trap/SMI on PORT 0064h read
1 enable trap/SMI on PORT 0060h write
0 enable trap/SMI on PORT 0060h read
See Also: #0913,#0923
Format of PCI Configuration Data for Intel 82557:
Offset Size Description (Table 0925)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 1229h) (see #0793)
10h DWORD base address of memory-mapped Control/Status Registers (4K)
(see #0926)
14h DWORD base address of I/O-mapped Control/Status Registers (32 ports)
18h DWORD base address of Flash memory (1M)
40h 192 BYTEs unused
See Also: #0888
Format of Intel 82557 Control/Status Registers:
Offset Size Description (Table 0926)
00h WORD SCB status word
02h WORD SCB command word
04h DWORD SCB general pointer
08h DWORD PORT
0Ch WORD Flash control register
0Eh WORD EEPROM control register
10h DWORD MDI control register
14h DWORD Early RCV Interrupt Rx byte count (RXBC) register
Note: see 64434604.pdf for additional details
See Also: #0926
Format of PCI Configuration Data for Intel 82441FX:
Offset Size Description (Table 0927)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 1237h) (see #0793)
40h 16 BYTEs reserved
50h WORD PMC Configuration (see #0928)
52h BYTE deturbo counter control
when deturbo mode is selected (see PORT 0CF9h), the chipset
places a hold on the memory bus for a fraction of the
time inversely proportional to the value in this register
(i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.)
53h BYTE DBX buffer control (see #0929)
54h BYTE auxiliary control (see #0930)
55h WORD DRAM Row Type (see #0931)
57h BYTE DRAM Control (see #0932)
58h BYTE DRAM Timing (see #0933)
59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #0902)
60h 8 BYTEs DRAM Row Buondary registers 0-7
each register N indicates cumulative amount of memory in rows
0-N (each 64 bits wide), in 8M units
68h BYTE Fixed DRAM Hole Control
69h 7 BYTEs reserved
70h BYTE Multi-Transaction Timer
number of PCLKs guaranteed to the current agent before the
82441 will grant the bus to another PCI agent on request
71h BYTE CPU Latency Timer (see #0934)
72h BYTE System Management RAM control (see #0906)
73h 29 BYTEs reserved
90h BYTE Error Command (see #0935)
91h BYTE Error Status (see #0936)
92h BYTE reserved
93h BYTE Turbo Reset Control (see #0937)
94h 108 BYTEs reserved
See Also: #0888,#0892
Bitfields for Intel 82441FX PMC Configuration Register:
Bit(s) Description (Table 0928)
15 WSC Protocol Enable
14 Row Select/Extra Copy select (read-only)
=1 pins on PMC configured as two additional row selects (6/7)
=0 extra copy of two lowest memory address bits enabled
13-10 reserved
9-8 host frequence select
00 reserved
01 60 MHz
10 66 MHz
11 reserved
7 reserved
6 ECC/Parity TEST enable
5-4 DRAM Data Integrity Mode
00 no parity/ECC
01 parity generated and checked
10 ECC generated and checked, correction disabled
10 ECC generated and checked, correction enabled
3 reserved
2 In-Order Queue size (0=one, 1=four)
1-0 reserved
See Also: #0927,#0929
Bitfields for Intel 82441FX DBX buffer control register:
Bit(s) Description (Table 0929)
7 enable delayed transactions
6 enable CPU-to-PCI IDE posting
5 enable USWC Write Post during I/O Bridge access
4 disable PCI Delayed Transaction timer
3 enable CPU-to-PCI Write Post
2 enable PCI-to-DRAM pipeline
1 enable PCI Burst Write Combining
0 enable Read-Around-Write
See Also: #0927,#0928
Bitfields for Intel 82441FX auxiliary control register:
Bit(s) Description (Table 0930)
7 enable RAS precharge
6-2 reserved
1 Lower Memory Address Buffer Set A
=0 8mA
=1 12mA
0 reserved
See Also: #0927
Bitfields for Intel 82441FX DRAM Row Type register:
Bit(s) Description (Table 0931)
15-14 row 7 DRAM type
13-12 row 6 DRAM type
11-10 row 5 DRAM type
9-8 row 4 DRAM type
7-6 row 3 DRAM type
5-4 row 2 DRAM type
3-2 row 1 DRAM type
1-0 row 0 DRAM type
00 fast page-mode DRAM
01 EDO DRAM
10 BEDO DRAM
11 empty row
See Also: #0927,#0932
Bitfields for Intel 82441FX DRAM Control register:
Bit(s) Description (Table 0932)
7 reserved
6 enable DRAM Refresh Queue
5 enable DRAM EDO Auto-Detect Mode
4 DRAM Refresh Type
=0 CAS before RAS
=1 RAS only
3 reserved
2-0 DRAM refresh rate
000 disabled
001 normal (as set by PMCCFG register)
01x reserved
1xx reserved
111 fast refresh (every 32 host clocks)
See Also: #0927,#0931,#0933
Bitfields for Intel 82441FX DRAM Timing register:
Bit(s) Description (Table 0933)
7 reserved
6 enable WCBR Mode
5-4 DRAM Read Burst Timing
BEDO EDO FPM
00 x333 x444 x444
01 x222 x333 x444
10 x222 x222 x333
11 res. res. res.
3-2 DRAM Write Burst Timing
(B)EDO FPM
00 x444 x444
01 x333 x444
10 x333 x333
11 x222 x333
1 RAS-to-CAS delay
=1 one clock
=0 zero clocks
0 insert one MA Wait State
See Also: #0927,#0932
Bitfields for Intel 82441FX CPU Latency Timer register:
Bit(s) Description (Table 0934)
7-5 reserved
4-0 snoop stall count value
See Also: #0927
Bitfields for Intel 82441FX Error Command register:
Bit(s) Description (Table 0935)
7-5 reserved
4 enable SERR# on receiving Target Abort
3 enable SERR# on PCI Parity Error (PERR#)
2 reserved
1 enable SERR# on receiving multiple-bit ECC/Parity error
0 enable SERR# on receiving single-bit ECC error
See Also: #0927,#0936
Bitfields for Intel 82441FX Error Status register:
Bit(s) Description (Table 0936)
7-5 DRAM row causing first multi-bit error (read-only)
4 multiple-bit uncorrectable error detected
write 1 to this bit to clear it
3-1 DRAM row causing first single-bit error (read-only)
0 single-bit correctable ECC error detected
write 1 to this bit to clear it
See Also: #0927,#0935
Bitfields for Intel 82441FX Turbo Reset Control register:
Bit(s) Description (Table 0937)
7-4 reserved
3 enable BIST on hard reset
2 reset CPU
1 reset mode
0 soft reset
.NG limit reached, continued in next section...