Int 1A Fn B10A - Pci Bios V2.0c+ - Read Configuration Dword (intel Devices) (Cont.)
48h BYTE ISA Address Decoder Control (see #0865)
49h BYTE ISA Address Decoder ROM Block Enable (see #0866)
4Ah BYTE ISA Address Decoder Bottom of Hole (address bits 23-16)
4Bh BYTE ISA Address Decoder Top of Hole (address bits 23-16)
4Ch BYTE ISA Controller Recovery Time (see #0883)
4Dh BYTE ISA Clock Divisor (see #0867)
4Eh BYTE Utility Bus Chip Select Enable A (see #0868)
4Fh BYTE Utility Bus Chip Select Enable B (see #0869)
50h 4 BYTEs reserved
54h BYTE MEMCS# Attribute Register #1 (see #0870)
attributes for 16K blocks from C0000h-CFFFFh
55h BYTE MEMCS# Attribute Register #2 (see #0870)
attributes for 16K blocks from D0000h-DFFFFh
56h BYTE MEMCS# Attribute Register #3 (see #0870)
attributes for 16K blocks from E0000h-EFFFFh
57h BYTE (82378) Scatter/Gather Relocation Base Adress (see #0871)
(82379AB) reserved
58h 8 BYTEs reserved
60h BYTE (82378ZB) IRQ0# Route Control (see #0872)
61h BYTE (82378ZB) IRQ1# Route Control (see #0872)
62h BYTE (82378ZB) IRQ2# Route Control (see #0872)
63h BYTE (82378ZB) IRQ3# Route Control (see #0872)
64h 12 BYTEs reserved
70h BYTE (82378) reserved
(82379AB, write-only) PIC/APIC Configuration Control
(see #0873)
71h BYTE (82378) reserved
(82379AB, write-only) APIC Base Address Relocation
(see #0874,MEM FEC00000h)
72h 14 BYTEs reserved
80h WORD BIOS timer base address (see PORT 0078h)
bits 15-2 are bits 15-2 of BIOS timer port address
bit 1: reserved (0)
bit 0: timer enabled (if disabled, other bits ignored)
82h 30 BYTEs unused???
A0h BYTE SMI Control (see #0875)
A1h BYTE reserved
A2h WORD SMI Enable (see #0876)
A4h DWORD System Event Enable (SEE) (see #0877)
A8h BYTE Fast-Off Timer (in minutes)
A9h BYTE reserved
AAh WORD active SMI Requests (see #0878)
ACh BYTE (82378ZB) Clock Throttle STPCLK# Low Timer
duration of STPCLK# low period in 32 microsecond units
ADh BYTE reserved
AEh BYTE (82378ZB) Clock Throttle STPCLK# High Timer
duration of STPCLK# high period in 32 microsecond units
AFh 81 BYTEs reserved
See Also: #0851,#0911,PORT 040Ah"82378ZB"
Bitfields for Intel 82378/82379 PCI Control:
Bit(s) Description (Table 0861)
7 reserved (0)
6 DMA Reserved Page Register Aliasing Control
=0 alias PORT 80h-8Fh to PORT 90h-9Fh
5 Interrupt Acknowledge Enable
=0 ignore INTA cycles on the PCI bus, but still allow 8259 register
access and poll-mode functions
4-3 Subtractive Decoding Sample Point
00 slow sample point
01 typical
10 fast sample point
11 reserved
2 PCI Posted Write Buffer Enable
1 ISA Master Line Buffer Configuration
=0 single-transaction mode
=1 eight-byte mode for ISA bus master transfers
0 DMA Line Buffer Configuration
=0 single-transaction mode
=1 eight-byte mode
See Also: #0860,#0862
Bitfields for Intel 82378/82379 PCI Arbiter Control:
Bit(s) Description (Table 0862)
7-5 reserveed (0)
4-3 Master Retry Timer
00 disabled (retries never masked)
01 retries unmasked after 16 PCICLKs
10 retries unmasked after 32 PCICLKs
11 retries unmasked after 64 PCICLKs
2 Bus Park
=1 park CPUREQ# on PCI bus when 82378 detects PCI bus idle
1 Bus Lock
=0 resource lock
=1 Bus lock
0 Guaranteed Access Time
=1 ISA bus masters are guaranteed 2.5 microsecond CHRDY time-out
See Also: #0860,#0861
Bitfields for Intel 82378/82379 PCI Arbiter Priority Control:
Bit(s) Description (Table 0863)
7 bank 3 rotate control
6 bank 2 rotate control
5 bank 1 rotate control
4 bank 0 rotate control
3 bank 2 fixed priority mode select B
2 bank 2 fixed priority mode select A
1 bank 1 fixed priority mode select
0 bank 0 fixed priority mode select
Note: if both 'rotate' and 'fixed' bits are set for a given bank,
that bank will be in rotating-priority mode
See Also: #0860,#0862
Bitfields for Intel 82378/82379 MEMCS# Control Register:
Bit(s) Description (Table 0864)
7-5 reserved (0)
4 MEMCS# Master Enable
3 write enable for 0F0000h-0FFFFFh
2 read enable for 0F0000h-0FFFFFh
1 write enable for 080000h-09FFFFh
0 read enable for 080000h-09FFFFh
See Also: #0860
Bitfields for Intel 82378/82379 ISA Address Decoder Control Register:
Bit(s) Description (Table 0865)
7-4 ISA memory cycle forwarding to PCI
0000-1111 = 1M-16M top of ISA memory; any accesses above programmed
limit are forwarded to PCI bus
3-0 ISA/DMA memory cycle to PCI bus enables
bit 3: 896K-960K (E000h-EFFFh)
bit 2: 640K-768K (A000h-BFFFh)
bit 1: 512K-640K (8000h-9FFFh)
bit 0: 0K-512K (0000h-7FFFh)
See Also: #0860,#0866
Bitfields for Intel 82378/82379 ISA Address Decoder ROM Block Enable:
Bit(s) Description (Table 0866)
7 enable 880K-896K (EC00h-EFFFh)
6 enable 864K-880K (E800h-EBFFh)
5 enable 848K-864K (E400h-E7FFh)
4 enable 832K-848K (E000h-E3FFh)
3 enable 816K-832K (DC00h-DFFFh)
2 enabel 800K-816K (D800h-DBFFh)
1 enable 784K-800K (D400h-D7FFh)
0 enable 768K-784K (D000h-D3FFh)
Note: ISA accesses within any enabled ranges are forwarded to the PCI bus
See Also: #0860,#0865
Bitfields for Intel 82378/82379 ISA Clock Divisor Register:
Bit(s) Description (Table 0867)
7 reserved (0)
6 enable positive decode of upper 64K BIOS at 000F0000h-000FFFFFh,
FFEF0000h-FFEFFFFFh, and FFFF0000h-FFFFFFFFh
5 coprocessor error enable
=1 FERR# is driven onto IRQ13
4 IRQ12/Mouse Function Enable
=0 standard IRQ12
=1 mouse
3 RSTDRV enable
=1 assert RSTDRV until this bit cleared (for use in changing ISA bus
speed)
2-0 PCICLK-to-ISA SYSCLK divisor
000 4
001 3
other reserved
See Also: #0860,#0865
Bitfields for Intel 82378/82379 Utility Bus Chip Select A Register:
Bit(s) Description (Table 0868)
7 extended BIOS enable (decode accesses to FFF80000h-FFFDFFFFh)
6 lower BIOS enable (decode accesses to E0000h-EFFFFh,
FFEE0000h-FFEEFFFFh, and FFFE0000h-FFFEFFFFh)
5 (82378ZB) floppy disk primary/secondary address select
=1 use secondary address range
4 (82378ZB) IDE Decode enable
3,2 floppy disk address locations enable
1 keyboard controller address location enable
enables I/O addresses 60h,62h,64h,66h (82378ZB) or 60h/64h (82379AB)
0 RTC address location enabled
=1 enable decode of I/O ports 70h-77h
See Also: #0860,#0885,#0869
Bitfields for Intel 82378ZB/82379 Utility Bus Chip Select B Register:
Bit(s) Description (Table 0869)
7 configuration RAM decode enable
=1 permit write accesses to I/O port 0C00h and r/w to ports 08xxh
6 enable PORT 0092h
5-4 parallel port enable
00 LPT1 (ports 03BCh-03BFh)
01 LPT2 (ports 0378h-037Fh)
10 LPT3 (ports 0278h-027Fh)
11 disabled
3-2 serial port B enable
00 COM1 (03F8h-03FFh)
01 COM2 (02F8h-02FFh)
10 reserved
11 port B disabled
1-0 serial port A enable
00 COM1 (03F8h-03FFh)
01 COM2 (02F8h-02FFh)
10 reserved
11 port A disabled
Note: if both serial ports are set to the same address, port B is disabled
See Also: #0860,#0868,PORT 0092h
Bitfields for Intel 82378/82379 MEMCS# Attribute Register 1/2/3:
Bit(s) Description (Table 0870)
7 write-enable xC000h-xFFFFh expansion ROM
6 read-enable xC000h-xFFFFh expansion ROM
5 write-enable x8000h-xBFFFh expansion ROM
4 read-enable x8000h-xBFFFh expansion ROM
3 write-enable x4000h-x7FFFh expansion ROM
2 read-enable x4000h-x7FFFh expansion ROM
1 write-enable x0000h-x3FFFh expansion ROM
0 read-enable x0000h-x3FFFh expansion ROM
Note: x = C/D/E depending on the attribute register
See Also: #0860
Bitfields for Intel 82378ZB Scatter Gather Relocation Base Address:
Bit(s) Description (Table 0871)
7-0 bits 15-8 of base address for scatter/gather I/O ports
(default 04h; low 8 bits of address are always 10h-3Fh)
See Also: #0860,#0870,#0872,PORT 040Ah"82378ZB",#P038
Bitfields for Intel 82378/82379 PCI IRQ Route Control Register:
Bit(s) Description (Table 0872)
7 disable IRQ routing
6-4 reserved (0)
3-0 ISA IRQ number to which to route the PCI IRQ
Note: IRQs 0-2, 8, and 13 are reserved
See Also: #0860,#0911
Bitfields for Intel 82379AB PIC/APIC Configuration Control Register:
Bit(s) Description (Table 0873)
7-2 reserved
1 SMI Routing Control
=1 SMI via APIC
=0 SMI via SMI# signal
0 INT Routing Control
=1 INT disabled (requires that APIC be enabled)
=0 INT enabled
See Also: #0860,#0874
Bitfields for Intel 82379AB/82371 APIC Base Address Relocation:
Bit(s) Description (Table 0874)
7 reserved
6 (82379AB) reserved
6 (82371) A12 mask
=1 ignore address bit 12 in APIC address
5-0 bits 15-10 of APIC memory address (ORed with FEC00000h to form base
address)
See Also: #0860,#0911,#0873,MEM FEC00000h
Bitfields for Intel 82378/82379 SMI Control Register:
Bit(s) Description (Table 0875)
7 reserved
6 (82378) reserved
(82379) require Stop Grant bus cycle before asserting STPCLK#
5-4 reserved
3 Fast-Off Timer freeze
2 STPCLK# scaling enable
=1 enable Clock Throttle bytes in PCI configuration space
1 STPCLK# signal enable
=1 assert STPCLK# on read from PORT 00B2h
0 SMI# Gate
=1 enable SMI# on system management interrupt
Notes: bit 1 is cleared either with an explicit write of 0 here, or by any
write to PORT 00B2h
bit 0 does not affect the recording of SMI events, so a pending SMI
will cause an immediate SMI# when the bit is set
See Also: #0860,#0876,#0877,#0920,PORT 00B2h
Bitfields for Intel 82371/82378/82379 SMI Enable Register:
Bit(s) Description (Table 0876)
15-9 reserved
8 (82371SB only) Legacy USB SMI enable
7 APMC Write SMI enable
=1 generate SMI on write to PORT 00B2h
6 EXTSMI# SMI enable
5 Fast-Off Timer SMI enable
4 IRQ12 (PS/2 mouse) SMI enable
3 IRQ8 (RTC alarm) SMI enable
2 IRQ4 (COM1/COM3) SMI enable
1 IRQ3 (COM2/COM4) SMI enable
0 IRQ1 (keyboard) SMI enable
See Also: #0860,#0875,#0877,#0911,PORT 00B2h
Bitfields for Intel 82371/82378/82379 System Event Enable Register:
Bit(s) Description (Table 0877)
31 Fast-Off SMI enable (system and break events)
30 (82379 only) Fast-Off Interrupt Enable (break events only)
30 (82371 only) INTR enable (break events only)
29 Fast-Off NMI enable (system and break events)
28 (82371SB only) Fast-Off APIC enable (break events only)
27 (82379 only) Fast-Off COM enable (system events only)
26 (82379 only) Fast-Off LPT enable (system events only)
25 (82379 only) Fast-Off Drive enable (system events only)
24 (82379 only) Fast-Off DMA enable (system events only)
23-16 reserved
15-3 Fast-Off IRQ (15-3) enable (system and break events)
2 reserved
1-0 Fast-Off IRQ (1-0) enable (system and break events)
Note: any enabled system event restarts the Fast-Off Timer, thus preventing
a Fast-Off powerdown; any enabled break event awakens the system from
powerdown
See Also: #0860,#0875,#0876,#0878,#0911
Bitfields for Intel 82371/82378/82379 SMI Request Register:
Bit(s) Description (Table 0878)
15-9 reserved
8 (82371SB only) Legacy USB SMI status
7 APM SMI Status (write to PORT 00B2h triggered SMI)
6 EXTSMI# SMI Status (EXTSMI# line triggered SMI)
5 Fast-Off Timer expired
4 IRQ12 triggered SMI
3 IRQ8 triggered SMI
2 IRQ4 triggered SMI
1 IRQ3 triggered SMI
0 IRQ1 triggered SMI
Note: software must explicitly reset the appropriate bits
See Also: #0860,#0877,#0911
Format of PCI Configuration data for Intel 82425EX PSC:
Offset Size Description (Table 0879)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 0486h)
40h BYTE PCI control register (see #0880)
41h 3 BYTEs ???
44h BYTE host device control register (see #0881)
.NG limit reached, continued in next section...