Int 1A Fn B10A - Pci Bios V2.0c+ - Read Configuration Dword (intel Devic [X]
AX = B10Ah subfn 8086h
BH = bus number
BL = device/function number (bits 7-3 device, bits 2-0 function)
DI = register number (0000h-00FFh) (see #0798)
Return: CF clear if successful
ECX = dword read
CF set on error
AH = status (00h,87h) (see #0653)
EAX, EBX, ECX, and EDX may be modified
all other flags (except IF) may be modified
Notes: this function may require up to 1024 byte of stack; it will not enable
interrupts if they were disabled before making the call
the meanings of BL and BH on entry were exchanged between the initial
drafts of the specification and final implementation
See Also: AX=B10Ah,AX=B10Ah/SF=1106h,AX=B10Dh
Format of PCI Configuration data for Intel 82375 EISA Bridge:
Offset Size Description (Table 0850)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 0482h)
(revision numbers: 03h = 82375EB, 04h = 82375SB)
40h BYTE PCI Control
!!!intel\29047704.pdf pg. 32
41h BYTE PCI Arbiter Control
42h BYTE PCI Arbiter Priority Control
43h BYTE PCI Arbiter Priority Control Extension
44h BYTE MEMCS# Control
45h BYTE MEMCS# Bottom of Hole
46h BYTE MEMCS# Top of Hole
47h BYTE MEMCS# Top of Memory
48h WORD EISA Address Decode Control 1
4Ah 2 BYTEs reserved
4Ch BYTE ISA I/O Recovery Time Control
4Dh 7 BYTEs reserved
54h BYTE MEMCS# Attribute Register #1
55h BYTE MEMCS# Attribute Register #2
56h BYTE MEMCS# Attribute Register #3
57h BYTE reserved
58h BYTE PCI Decode Control
59h BYTE reserved
5Ah BYTE EISA Address Decode Control 2
5Bh BYTE reserved
5Ch BYTE EISA-to-PCI Memory Region Attributes
5Dh 3 BYTEs reserved
60h 4 DWORDs EISA-to-PCI Memory Region Address registers 1-4
70h 4 DWORDs EISA-to-PCI I/O Region Address registers 1-4
80h WORD BIOS Timer base address
82h 2 BYTEs reserved
84h BYTE EISA Latency Timer Control Register
85h 3 BYTEs reserved
88h DWORD PCEB Test Control Register ("DO NOT WRITE")
8Ch 116 BYTEs reserved
See Also: #0798,#0851
Format of PCI Configuration data for Intel 82434LX/NX Cache/DRAM Controller:
Offset Size Description (Table 0851)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 04A3h)
(revision numbers: 01h/03h are 82434LX, 1xh are 82434NX)
(command register only supports bits 8,6,2,1,0)
40h 16 BYTEs unused (hard-wired to 00h)
44h BYTE ??? (AMI BIOS writes 00h)
45h BYTE ??? (AMI BIOS writes 00h)
50h BYTE Host CPU Selection (see #0852)
51h BYTE deturbo frequency control register
when deturbo mode is selected (see PORT 0CF9h), the chipset
places a hold on the memory bus for a fraction of the
time inversely proportional to the value in this register
by comparing it against a free-running 8-bit counter counting
at 1/8 the CPU clock speed
(i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.)
(only bits 7-6 writable, bits 5-0 hardwired to 0)
52h BYTE Secondary Cache Control (see #0853)
53h BYTE Host Read/Write Buffer Control (see #0854)
54h BYTE PCI Read/Write Buffer Control
bits 7-3: reserved
bit 2: LBXs connected to TRDY#
bit 1: enable PCI burst writes
bit 0: enable PCI-to-memory posted writes
55h 2 BYTEs reserved
57h BYTE DRAM Control (see #0855)
58h BYTE DRAM Timing (see also #0901)
bits 7-2: reserved
bit 1: (NX only) RAS# Wait State
bit 0: CAS# Wait State (one extra wait state before CAS#
within burst cycle)
59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #0902)
60h 8 BYTEs DRAM Row Boundary registers 0-7
(chip revisions numbered < 10h [LX] only support six rows of
DRAM)
each register N indicates the amount of cumulative amount of
memory in SIMM banks 0-N, in multiples of 1M; offset 67h
(65h on 82434LX's) contains the total amount of memory
installed in the system; on the 82434NX, two additional
bits are concatenated to each row boundary from the DRAM Row
Boundary Extension registers to allow up to 1024M of memory
to be specified (though only 512M are supported)
68h 4 BYTEs (NX only) DRAM Row Boundary Extension registers
each nybble is concatenated with the corresponding DRAM Row
Boundary register to form a 12-bit boundary value (of which
only the low 10 bits are actually used)
6Ch DWORD reserved (hardwired to 00000000h)
70h BYTE Error Command (see #0856)
71h BYTE Error Status (see #0857)
72h BYTE System Management RAM control (see also #0906)
bits 7-6: reserved
bit 5: map SMM-mode memory (64K) into address space when bits
2-0 = 010 (default 3000h:0000h; can be changed by
first SMM event)
bit 4: close SMRAM space (allows data accesses to be forwarded
to PCI bus while execuding SMM code)
bit 3: lock SMRAM space (can't be cleared by software)
bits 2-0: SMRAM memory address (010 = Axxxxh, 011 = Bxxxxh)
73h 5 BYTEs reserved
78h WORD Memory Space Gap
bit 15: enable ISA hole
bits 14-12: size of ISA hole in MB (less 1); must be power of 2
bits 11-8: reserved
bits 7-4: bottom of ISA memory hole in MB
(must be multiple of gap size)
bits 3-0: reserved
7Ah 2 BYTEs reserved
7Ch DWORD Frame Buffer Range (see #0858)
80h 128 BYTEs reserved
Note: the 82434NX is part of the Intel Neptune chipset
See Also: #0860,#0879
Bitfields for Intel 82434LX/NX Host CPU Selection:
Bit(s) Description (Table 0852)
7-5 host CPU type
LX: hardwired to 100 (Pentium)
NX: "reserved" (101 on RB's system)
4-3 reserved
2 enable L1 cache
1-0 Host Operating Frequency (set according to external bus speed)
00: reserved
01: 50 MHz
10: 60 MHz
11: 66 MHz
(LX: bit 1 reserved, only 60/66 MHz supported)
See Also: #0851,#0853
Bitfields for Intel 82434LX/NX Secondary Cache Control:
Bit(s) Description (Table 0853)
7-6 secondary cache size
00 none
01 reserved
10 256K
11 512K
5 SRAM type
0 standard SRAMs
1 burst SRAMs
4 secondary cache allocation
0 cache only CPU reads of memory with CACHE# asserted
1 cache all CPU reads of cacheable memory
3 Cache Byte Control
0 use single write enable and per-byte select lines
1 use per-byte write enables on the cache
2 (NX only) SRAM connectivity
0 disable CCS[1:0]# / CCS1# functionality
1 enable CCS[1:0]# functionality to de-select async SRAMs, placing them
in a low-power standby mode
1 enable CCS1# functionality for burst SRAMs, indicating the lack of an
external address latch
1 (LX only) Secondary Cache Write Policy
0 write-through
1 write-back (NX is always in write-back mode)
0 Secondary Cache Enable
See Also: #0851,#0854
Bitfields for Intel 82434LX/NX Host Read/Write Buffer Control:
Bit(s) Description (Table 0854)
7-4 reserved
3 enable read-around-write
2 reserved
1 enable CPU-to-PCI posted writes
0 (LX only) enable CPU-to-memory posted writes
(NX always posts memory writes)
See Also: #0851,#0853
Bitfields for Intel 82434LX/NX DRAM Control:
Bit(s) Description (Table 0855)
7-6 (NX only) DRAM burst timing
00 X-4-4-4 read/write (default)
01 X-4-4-4 read, X-3-3-3 write
10 reserved
11 X-3-3-3 read/write
5 parity error mask
4 0-Active RAS# mode
3 SMRAM enable (must be set to enable reg 72h)
2 Burst-of-Four Refresh
1 Refresh Type
=0 RAS#-only
=1 CAS#-before-RAS#
0 DRAM Refresh Enable
See Also: #0851
Bitfields for Intel 82434LX/NX Error Command register:
Bit(s) Description (Table 0856)
7 assert SERR# on receiving target abort
6 assert SERR# on PCI data-write parity error
5 (NX only) assert SERR# on PCI data-read parity error
4 (NX only) assert SERR# on PCI address parity error
3 (NX only) assert PERR# on data parity error
2 enable L2 cache parity
1 enable SERR# on DRAM/L2 cache data parity error
0 assert PEN# on data reads; allow CPU to signal parity error via PCHK#
Notes: PCI command register bit 6 is master enable for bit 3;
PCI cmd bits 6 and 8 are the master enable for bits 7-4 and 1
bits 1-0 = 10 is not permitted
See Also: #0851,#0857
Bitfields for Intel 82434LX/NX Error Status register:
Bit(s) Description (Table 0857)
7 reserved
6 PCI-write detected parity error
5 (NX only) PCI-read detected parity error
4 (NX only) PCI address parity error detected
3 main memory data parity error
2 L2 cache data parity error
1 reserved
0 Shutdown cycle detected
Note: clear status bits by writing a 'one' bit to each bit to be cleared
See Also: #0856,#0851
Bitfields for Intel 82434LX/NX Frame Buffer Range register:
Bit(s) Description (Table 0858)
31-20 buffer offset (in 1MB increments; must be multiple of buffer set set
by bits 3-0)
19-14 reserved
13 enable byte merging
12 128K VGA-range Attribute Enable
when set, bits 13,9,7 also apply to VGA memory range (Axxxx-Bxxxx)
11-10 reserved
9 no lock requests
8 reserved
7 enable transparent bufer writes
6-4 reserved
3-0 buffer size in MB (less 1); must be power of 2
Note: if bits 31-20=0, the frame buffer feature is disabled
See Also: #0851
Format of PCI Configuration data for Intel 82424 Cache Controller:
Offset Size Description (Table 0859)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 0483h)
40h BYTE bus number
41h BYTE subordinate bus number
42h BYTE disconnect timer
50h BYTE host CPU selection
51h BYTE deturbo frequency control
when deturbo mode is selected (see PORT 0CF9h), the chipset
places a hold on the memory bus for a fraction of the
time inversely proportional to the value in this register
(i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.)
52h BYTE secondary cache control
53h BYTE write buffer control
54h BYTE PCI features control
55h BYTE DRAM Operation Mode Select
56h BYTE System Exception Handling
57h BYTE SMM Control Register
58h BYTE reserved
59h 7 BYTEs Programmable Attribute Map registers 0-6 (see also #0902)
60h 4 BYTEs DRAM Row Boundary registers 0-3
each register N indicates amount of memory in rows 0-N (each
row is 64 bits wide)
boundary register 3 (offset 63h) contains the total system
memory, which may not exceed 128M
64h 4 BYTEs unused???
68h WORD Memory Hole-0
6Ah WORD Memory Hole-1
Note: the above field names are those given by EduWARE's PCI Configuration
Manager v1.2
See Also: #0851,#0879,#0892
Format of PCI Configuration data for Intel 82378 and 82379 ISA Bridges:
Offset Size Description (Table 0860)
00h 64 BYTEs header (see #0798)
(vendor ID 8086h, device ID 0484h)
(revision ID:
bits 7-4: reserved
bits 3-0: revision
0011 82378ZB A0-step
1000 82379AB A0-step)
40h BYTE PCI Control (see #0861)
41h BYTE PCI Arbiter Control (see #0862)
42h BYTE PCI Arbiter Priority Control (see #0863)
43h BYTE (82378ZB) PCI Arbiter Priority Control Extension Register
bit 0: bank 3 fixed priority mode select (see also #0863)
=0 REQ2# has higher priority
=1 REQ3# has higher priority
44h BYTE MEMCS# Control (see #0864)
45h BYTE MEMCS# Bottom of Hole (address bits 23-16)
46h BYTE MEMCS# Top of Hole (address bits 23-16)
47h BYTE MEMCS# Top of Memory
(address bits 28-21 == size in 2M increments, less 1)
.NG limit reached, continued in next section...