Int 1A Fn B10A - Pci Bios V2.0c+ - Read Configuration Dword (via Technol [X]
AX = B10Ah subfn 1106h
BH = bus number
BL = device/function number (bits 7-3 device, bits 2-0 function)
DI = register number (0000h-00FFh) (see #0798)
Return: CF clear if successful
ECX = dword read
CF set on error
AH = status (00h,87h) (see #0653)
EAX, EBX, ECX, and EDX may be modified
all other flags (except IF) may be modified
Notes: this function may require up to 1024 byte of stack; it will not enable
interrupts if they were disabled before making the call
the meanings of BL and BH on entry were exchanged between the initial
drafts of the specification and final implementation
See Also: AX=B10Ah,AX=B10Ah/SF=8086h
Format of AMD-645 Peripheral Bus Controller, function 1 (IDE Control) data:
Offset Size Description (Table 0844)
00h 64 BYTEs header (see #0798)
(vendor ID 1106h [VIA Technologies], device ID 0571h)
10h DWORD primary data/command base address
14h DWORD primary control/status base address
18h DWORD secondary data/command base address
1Ch DWORD secondary control/status base address
20h DWORD bus master control base address (default 0000CC01h)
40h BYTE chip enable
41h BYTE IDE configuration
42h BYTE reserved ("do not program")
43h BYTE FIFO configuration
44h BYTE miscellaneous control 1
45h BYTE miscellaneous control 2
46h BYTE miscellaneous control 3
47h BYTE unused???
48h DWORD drive timing control
4Ch BYTE address setup time
4Dh BYTE reserved ("do not program")
4Eh BYTE secondary non-01F0h port access timing
4Fh BYTE primary non-01F0h port access timing
50h DWORD UltraDMA/33 extended timing control
54h 4 BYTEs reserved
58h DWORD "reserved" (appears to be an additional drive timing control)
5Ch 4 BYTEs ???
60h WORD primary sector size
62h 6 BYTEs reserved
68h WORD secondary sector size
6Ah 150 BYTEs reserved
!!!amd\21095a.pdf p.129
See Also: #0740,#0845,#0847
Format of AMD-645 Peripheral Bus Controller, function 0 (PCI-ISA bridge) data:
Offset Size Description (Table 0845)
00h 64 BYTEs header (see #0798)
(vendor ID 1106h, device ID 0586h)
40h BYTE ISA bus control
41h BYTE ISA Test Mode
42h BYTE ISA clock control
43h BYTE ROM Decode Control
44h BYTE keyboard controller control
45h BYTE Type F DMA control
46h BYTE Miscellaneous control 1
47h BYTE Miscellaneous control 2
48h BYTE Miscellaneous control 3
49h BYTE reserved
4Ah BYTE IDE interrupt routing
4Bh BYTE reserved
4Ch BYTE DMA/Master memory access control 1
4Dh BYTE DMA/Master memory access control 2
4Eh WORD DMA/Master memory access control 3
50h BYTE reserved ("do not program")
51h 3 BYTEs reserved
54h BYTE PIC IRQ Edge/Level selection
55h BYTE PnP Routing for external MIRQ0/1
56h BYTE PnP Routing for PCI INTB/INTA
57h BYTE PnP Routing for PCI INTD/INTC
58h BYTE PnP Routing for external MIRQ2
59h BYTE MIRQ pin configuration
5Ah BYTE XD Power-On Strap Options
5Bh BYTE internal RTC test mode
5Ch 4 BYTEs reserved
60h WORD distributed DMA, channel 0 base address/enable
62h WORD distributed DMA, channel 1 base address/enable
64h WORD distributed DMA, channel 2 base address/enable
66h WORD distributed DMA, channel 3 base address/enable
68h WORD reserved
6Ah WORD distributed DMA, channel 5 base address/enable
6Ch WORD distributed DMA, channel 6 base address/enable
6Eh WORD distributed DMA, channel 7 base address/enable
70h 144 BYTEs reserved
!!!amd\21095a.pdf p.125
See Also: #0740,#0846,#0844,#0847
Format of AMD-640 System Controller:
Offset Size Description (Table 0846)
00h 64 BYTEs header (see #0798)
(vendor ID 1106h, device ID 0595h)
0Dh BYTE latency timer (bits 7-3)
00h = 256*8 PCI clocks
01h = 1*8 PCI clocks
02h = 2*8 PCI clocks
other reserved
40h 16 BYTEs unused???
50h BYTE cache control 1
!!!amd\21090a.pdf p.107
51h BYTE cache control 2
52h BYTE non-cacheable control
53h BYTE system performance control
54h WORD non-cacheable region 1
56h WORD non-cacheable region 2
58h BYTE DRAM configuration register 1
59h BYTE DRAM configuration register 2
5Ah 6 BYTEs end of DRAM banks 0-5
60h BYTE DRAM type
61h BYTE shadow RAM control register 1
62h BYTE shadow RAM control register 2
63h BYTE shadow RAM control register 3
64h BYTE DRAM timing
65h BYTE DRAM control register 1
66h BYTE DRAM control register 2
67h BYTE 32-bit DRAM width control register
68h 2 BYTEs reserved
6Ah BYTE DRAM refresh counter
6Bh BYTE DRAM refresh control register
6Ch BYTE SDRAM control register
6Dh BYTE DRAM drive strength control register
6Eh BYTE ECC control register
6Fh BYTE ECC status register
70h BYTE PCI buffer control 1
71h BYTE CPU-to-PCI flow control 1
72h BYTE CPU-to-PCI flow control 2 (write-clear)
73h BYTE PCI target control
74h BYTE PCI initiator control
75h BYTE PCI arbitration control 1
76h BYTE PCI arbitration control 2
77h 137 BYTEs reserved
Note: the AMD-640 uses PCI configuration mechanism #1; bus/device/function
are always 00h/00h/00h
See Also: #0740,#0845
Format of AMD-645 Peripheral Bus Controller, function 2 (USB Controller) data:
Offset Size Description (Table 0847)
00h 64 BYTEs header (see #0798)
(vendor ID 1106h, device ID 3038h)
20h DWORD base address
40h BYTE miscellaneous control 1
41h BYTE miscellaneous control 2
42h 2 BYTEs reserved
44h 3 BYTEs reserved ("do not program")
47h BYTE reserved
48h 24 BYTEs reserved
60h BYTE USB release number (read-only, 10h)
61h 95 BYTEs reserved
C0h WORD USB legacy support (read-only, 2000h)
C2h 62 BYTEs reserved
!!!amd\21095a.pdf p.130
See Also: #0740,#0846,#0845,#0844,#0848
Format of AMD-645 Peripheral Bus Controller, function 3 (Power Mgmt) data:
Offset Size Description (Table 0848)
00h 64 BYTEs header (see #0798)
(vendor ID 1106h, device ID 3040h)
20h DWORD base address for I/O registers (see #0849)
40h BYTE pin configuration
41h BYTE genearl configuration
42h BYTE SCI interrupt configuration
43h BYTE reserved
44h WORD primary interrupt channel
46h WORD secondary interrupt channel
48h 8 BYTEs unused???
50h DWORD GP timer control
54h 13 BYTEs reserved
61h BYTE programming interface read value (value to be returned by
configuration register 09h) (write-only)
62h BYTE subclass read value (value to be returned by
configuration register 0Ah) (write-only)
63h BYTE base class read value (value to be returned by configuration
register 0Bh) (write-only)
64h 156 BYTEs reserved
!!!amd\21095a.pdf p.133
See Also: #0740,#0846,#0845,#0844,#0847,#0848
Format of AMD-645 Power Management Control/Status registers:
Offset Size Description (Table 0849)
00h WORD power management status (write-clear)
02h WORD power management enable
04h WORD power management control
06h 2 BYTEs unused???
08h DWORD power management timer
0Ch 4 BYTEs unused???
10h
!!!amd\21095a.pdf p.134
Note: this data structure is actually a range of I/O ports
See Also: #0848