Int 1A Fn B10A - Pci Bios V2.0c+ - Read Configuration Dword (Cont.)
92h BYTE (TI PCI1130) Device Control Register (see #0818)
93h BYTE (TI PCI1130) Buffer Control Register
800h 64+ BYTEs ExCa Socket Interface Registers (see #0811)
Format of ExCa memory-mapped registers:
Offset Size Description (Table 0811)
00h BYTE identification and revision register
01h BYTE interface status register
02h BYTE power control register
03h BYTE interrupt and general control
04h BYTE card status change
05h BYTE card status change interrupt configuration
06h BYTE address window enable
07h BYTE I/O window control register
08h WORD I/O window 0 start address
0Ah WORD I/O window 0 end address
0Ch WORD I/O window 1 start address
0Eh WORD I/O window 1 end address
10h WORD memory window 0 start address
12h WORD memory window 0 end address
14h WORD memory window 0 offset address
16h 2 BYTEs user-defined
18h WORD memory window 1 start address
1Ah WORD memory window 1 end address
1Ch WORD memory window 1 offset address
1Eh BYTE user-defined
1Fh BYTE reserved
20h WORD memory window 2 start address
22h WORD memory window 2 end address
24h WORD memory window 2 offset address
26h 2 BYTEs user-defined
28h WORD memory window 3 start address
2Ah WORD memory window 3 end address
2Ch WORD memory window 3 offset address
2Eh 2 BYTEs user-defined
30h WORD memory window 4 start address
32h WORD memory window 4 end address
34h WORD memory window 4 offset address
36h 10 BYTEs user-defined
---optional---
40h BYTE memory window 0 start address high byte
41h BYTE memory window 1 start address high byte
42h BYTE memory window 2 start address high byte
43h BYTE memory window 3 start address high byte
44h BYTE memory window 4 start address high byte
45h-7FFh user-defined
See Also: #0810
Bitfields for CardBus Socket Event Register:
Bit(s) Description (Table 0812)
0 CSTSCHG pin asserted (status change)
1 CCD1# (card detect 1) changed state
2 CCD2# (card detect 2) changed state
3 interface power cycle completed
31-4 reserved (0)
Note: the bits in this register are set by the bridge, and cleared by writing
a one into the bits one wishes to clear
See Also: #0810,#0813,#0815
Bitfields for CardBus Socket Event Mask Register:
Bit(s) Description (Table 0813)
0 write-protect (enable status-change interrupt on WriteProtect switch)
1 ready mask (allow status-change interrupt on Ready line change)
3-2 battery condition (allow status-change int on battery-condition change)
4 general wakeup enabled
5 binary audio mode enabled on CAUDIO pin
6 Pulse Width Modulation enabled on CAUDIO pin
(CAUDIO state undefined if both bits 5 and 6 set)
13-7 reserved (0)
14 Wakeup mask (enable wakeup events via status-change pin)
15 enable card interrupts via CINT# pin and wakeup events
31-16 reserved
See Also: #0810,#0812,#0814
Bitfields for CardBus Socket Present State Register:
Bit(s) Description (Table 0814)
0 CSTSCHG pin asserted (status change)
1 CCD1# (card detect 1) changed state
2 CCD2# (card detect 2) changed state
3 interface power cycle completed
4 16-bit PC card inserted
5 CardBus card inserted
6 card's interrupt pin asserted
7 card inserted but type can not be determined
8 data may have been lost due to abrupt card removal
9 attempted to apply Vcc voltage not supported by the card
10 card can accept Vcc = 5.0 volts
11 card can accept Vcc = 3.3 volts
12 card can accept Vcc = X.X volts
13 card can accept Vcc = Y.Y volts
27-14 reserved (0)
28 socket can accept Vcc = 5.0 volts
29 socket can accept Vcc = 3.3 volts
30 socket can accept Vcc = X.X volts
31 socket can accept Vcc = Y.Y volts
Note: bits 0-3 may be cleared by writing a 1 into the respective bits
See Also: #0810,#0812,#0813,#0816
Bitfields for CardBus Socket Force Event Register:
Bit(s) Description (Table 0815)
0 write-protect
1 ready
2 battery voltage detect 2
3 battery voltage detect 1
4 general wakeup
14-5 reserved (0)
15 enable card interrupts via CINT# pin
31-16 reserved
Note: this register can simulate events by forcing the values of some of the
bits in the Event Mask Register; any bit of this register which is
set to 1 forces the corresponding bit in the Mask Register to 1,
while bits set to 0 leave the corresponding bit unchanged
See Also: #0810,#0812,#0816
Bitfields for CardBus Socket Control Register:
Bit(s) Description (Table 0816)
2-0 Vpp control
000 power off
001 12.0 Volts
010 5.0 Volts
011 3.3 Volts
100 reserved (X.X Volts)
101 reserved (Y.Y Volts)
110 reserved
111 reserved
3 reserved (0)
6-4 Vcc control (as for Vpp, but 12.0V not supported)
31-7 reserved (0)
See Also: #0810,#0813,#0815
Bitfields for TI PCI1130 Card Control Register:
Bit(s) Description (Table 0817)
0 interrupt pending
1 speaker output enabled
2 reserved
3 enable status-change interrupt routing (to INTA# for socket A, INTB#
for socket B)
4 function interrupt routed to corresponding PCI interrupt pin
5 PCI interrupts enabled
6 ZOOM video mode enabled
7 Ring Indicator enabled on IRQ15/RI_OUT pin
See Also: #0810,#0818
Bitfields for TI PCI1130 Device Control Register:
Bit(s) Description (Table 0818)
0 reserved (0)
2-1 interrupt mode enable
00 no interrupt
01 ISA mode (direct IRQ routing)
10 serialized interrupt mode
11 reserved
4-3 reserved
5 3volt Socket Capable force bit
6 5volt Socket Capable force bit
7 reserved
See Also: #0810,#0817
Bitfields for PCI Configuration I/O base and limit:
Bit(s) Description (Table 0819)
3-0 (read-only) address decoding type
0000 16-bit
0001 32-bit
other reserved
7-4 bits 15-12 of I/O address range
See Also: #0798,#0820
Bitfields for PCI Configuration memory base and limit:
Bit(s) Description (Table 0820)
3-0 address decode type
0000 32-bit address decoder
0001 64-bit address decoder
other reserved
15-4 bits 31-20 of memory address range
See Also: #0798,#0819
Format of PCI Configuration Data for VLSI VL82C591 Host/PCI bridge:
Offset Size Description (Table 0821)
00h 64 BYTEs header (see #0798)
(vendor ID 1004h, device ID 0005h)
40h BYTE bus number
41h BYTE subordinate bus number
42h WORD reserved
44h 4 DWORDs reserved
54h 2 BYTEs device-specific configuration registers
56h WORD reserved
58h 2 BYTEs device-specific configuration registers
5Ah WORD reserved
5Ch 5 BYTEs device-specific configuration registers
...
FFh BYTE device-specific configuration register
See Also: #0798,#0656,#0822
Format of PCI Configuration data for VLSI VL82C593 PCI/ISA bridge:
Offset Size Description (Table 0822)
00h 64 BYTEs header (see #0798)
(vendor ID 1004, device ID 0006h)
40h 4 DWORDs reserved
50h 11 BYTEs device-specific configuration registers
5Bh BYTE reserved
5Ch 25 BYTEs device-specific configuration registers
75h 138 BYTEs reserved
FFh BYTE device-specific configuration register
See Also: #0798,#0821
Format of AMD Am53C974A PC-SCSI PCI configuration data:
Offset Size Description (Table 0823)
00h 64 BYTEs header (see #0798)
(vendor ID 1022h, device ID 2020h)
10h DWORD I/O base address (see PORT xxxxh"Am53C974A")
40h 16 BYTEs scratch registers
(used by AMD's PC-SCSI drivers as follows:
40h/41h SCSI configuration register 0 (see #0824,#0825)
...
4Eh/4Fh SCSI configuration register 7)
See Also: #0670
Bitfields for AMD Am53C974A Target Device Configuration Register:
Bit(s) Description (Table 0824)
15-14 reserved
13 "FSCSI" Fast SCSI drive is present
12-8 "SPD" synchronous period
7-4 synchronous offset (0 = asynchronous transfers)
3-1 SCSI bus status
0 target device is present and active
if 0, all other bits must be cleared to zero for target devices
See Also: #0823,#0825
Bitfields for AMD Am53C974A Host Configuration Register:
Bit(s) Description (Table 0825)
15-9 reserved
8 SCSI bus has been reset
7 starting BIOS number (bits 6-4) is valid
6-4 starting BIOS number (000 = BIOS drive 80h, 001 = drive 81h, etc)
3 this device is a SCSI host
2 protected-mode driver initialized
1 real-mode driver initialized
0 target device present
=0 indicates that this is a host if bit 3 is set
See Also: #0823,#0824
Format of PCI Configuration data for PC Technology RZ-1000 EIDE controller:
Offset Size Description (Table 0826)
00h 64 BYTEs header (see #0798)
(vendor ID 1042h, device ID 1000h)
10h DWORD base address for controller I/O registers
(set to 01F1h for primary controller, 0171h for secondary)
14h DWORD base address for controller digital I/O port
(set to 03F5h for primary, 0375h for secondary)
40h DWORD ???
bits 7-1: ???
bit 13: read-ahead mode enabled
(Read-Ahead is buggy on original RZ-1000, and is
thus typically disabled by clearing this bit)
bit 16: ???
44h DWORD ???
48h 8 BYTEs ???
50h 176 BYTEs unused???
Format of OpenHCI Host Controller memory-mapped registers:
Offset Size Description (Table 0827)
00h DWORD "HcRevision" OpenHCI revision (see #0828)
04h DWORD "HcControl" HC operating modes (see #0829)
08h DWORD "HcCommandStatus" command/status (see #0830)
0Ch DWORD "HcInterruptStatus" interrupt status (see #0831)
10h DWORD "HcInterruptEnable" enable interrupts (see #0832)
14h DWORD "HcInterruptDisable" disable interrupts (see #0832)
18h DWORD "HcHCCA" HC Communications Area (see #0833)
1Ch DWORD "HcPeriodCurrentED" Endpoint Descriptor addr (see #0834)
20h DWORD "HcControlHeadED" Control Endpoint Descriptor (see #0835)
24h DWORD "HcControlCurrentED" Control Endpoint Descriptor (see #0835)
28h DWORD "HcBulkHeadED" Bulk Endpoint Descriptor (see #0836)
2Ch DWORD "HcBulkCurrentED" Bulk Endpoint Descriptor (see #0836)
30h DWORD "HcDoneHead" last completed Xfer Descr. (see #0837)
34h DWORD "HcFmInterval" Frame bit-time interval (see #0838)
38h DWORD "HcFmRemaining" bit time remaining in Frame (see #0839)
3Ch DWORD "HcFmNumber" Frame Number (bits 15-0)
40h DWORD "HcPeriodicStart" earliest time to start periodic list
(bits 13-0)
44h DWORD "HcLSThreshold" threshold for Low Speed transaction
(bits 11-0)
48h DWORD "HcRhDescriptorA" Root Hub Descriptor A (see #0840)
4Ch DWORD "HcRhDescriptorB" Root Hub Descriptor B (see #0841)
50h DWORD "HcRhStatus" Root Hub status (see #0842)
54h N DWORDs "HCRhPortStatus[1-N]" Root Hub port status N (see #0843)
Note: OpenHCI reserves a full 4K page of the systems address space for its
memory-mapped registers
See Also: #0798,#0802,#F059
Bitfields for OpenHCI "HcRevision" register:
Bit(s) Description (Table 0828)
31-8 reserved
7-0 BCD OpenHCI specification number (10h = 1.0, 11h = 1.1)
Note: this register is read-only
See Also: #0827,#0829
Bitfields for OpenHCI "HcControl" register:
Bit(s) Description (Table 0829)
31-11 reserved
10 RWE enable Remote Wakeup feature
9 RWC controller supports Remote Wakeup signalling
8 IR Interrupt Routing
0 normal host bus interrupt
1 System Managment Interrupt
7-6 HCFS USB Host Controller Functional State
00 USBReset
01 USBResume
10 USBOperational
11 USBSuspend
5 BLE enable Bulk List processing in next frame
4 CLE enable Control List processing in next frame
3 IE enable Isochronous ED processing
.NG limit reached, continued in next section...