Int 1A Fn B10A - Pci Bios V2.0c+ - Read Configuration Dword [X]
AX = B10Ah
BH = bus number
BL = device/function number (bits 7-3 device, bits 2-0 function)
DI = register number (0000h-00FFh, must be multiple of 4) (see #0798)
Return: CF clear if successful
ECX = dword read
CF set on error
AH = status (00h,87h) (see #0653)
EAX, EBX, ECX, and EDX may be modified
all other flags (except IF) may be modified
Notes: this function may require up to 1024 byte of stack; it will not enable
interrupts if they were disabled before making the call
the meanings of BL and BH on entry were exchanged between the initial
drafts of the specification and final implementation
See Also: AX=B108h,AX=B109h,AX=B10Ah/SF=8086h,AX=B18Ah,INT 2F/AX=1684h/BX=304Ch
Format of PCI Configuration Data:
Offset Size Description (Table 0798)
00h WORD vendor ID (read-only) (see #0656 at AX=B102h)
FFFFh returned if requested device non-existent
02h WORD device ID (read-only)
04h WORD command register (see #0799)
06h WORD status register (see #0800)
08h BYTE revision ID
09h 3 BYTEs class code
bits 7-0: programming interface
bits 15-8: sub-class
bits 23-16: class code (see also #F059)
0Ch BYTE cache line size
0Dh BYTE latency timer
0Eh BYTE header type
bits 6-0: header format
00h other
01h PCI-to-PCI bridge
02h PCI-to-CardBus bridge
bit 7: multi-function device
0Fh BYTE Built-In Self-Test result (see #0801)
---header type 00h---
10h DWORD base address 0 (see #0802)
(OpenHCI) base address of host controller registers (see #0827)
14h DWORD base address 1
18h DWORD base address 2
1Ch DWORD base address 3
20h DWORD base address 4
24h DWORD base address 5
28h DWORD CardBus CIS pointer (read-only) (see #0809)
2Ch WORD subsystem vendor ID or 0000h
2Eh WORD subsystem ID or 0000h
30h DWORD expansion ROM base address (see #0803)
34h BYTE offset of capabilities list within configuration space (R/O)
(only valid if status register bit 4 set) (see #0804)
35h 3 BYTEs reserved
38h DWORD reserved
3Ch BYTE interrupt line
00h = none, 01h = IRQ1 to 0Fh = IRQ15
3Dh BYTE interrupt pin (read-only)
(00h = none, else indicates INTA# to INTD#)
3Eh BYTE minimum time bus master needs PCI bus ownership, in 250ns units
(read-only)
3Fh BYTE maximum latency, in 250ns units (bus masters only) (read-only)
40h 48 DWORDs varies by device (see #0821,#0822,#0851,#0879)
---header type 01h---
10h DWORD base address 0 (see #0802)
14h DWORD base address 1
18h BYTE primary bus number (for bus closer to host processor)
19h BYTE secondary bus number (for bus further from host processor)
1Ah BYTE subordinate bus number
1Bh BYTE secondary latency timer
1Ch BYTE I/O base (see #0819)
1Dh BYTE I/O limit (see #0819)
1Eh WORD secondary status
20h WORD memory base (see #0820)
22h WORD memory limit
24h WORD prefetchable memory base
26h WORD prefetchable memory limit
28h DWORD prefetchable base, upper 32 bits
2Ch DWORD prefetchable limit, upper 32 bits
30h WORD I/O base, upper 16 bits
32h WORD I/O limit, upper 16 bits
34h DWORD reserved
38h DWORD expansion ROM base address
3Ch BYTE interrupt line
3Dh BYTE interrupt pin (read-only)
3Eh WORD bridge control
40h 48 DWORDs varies by device (see #0821,#0822,#0851,#0879)
---header type 02h---
10h DWORD CardBus Socket/ExCa base address (see #0810)
bits 31-12: start address of socket interface register block
in 4K blocks
bits 11-0: reserved (0)
14h BYTE offset of capabilities list within configuration space (R/O)
(only valid if status register bit 4 set) (see #0804)
15h BYTE reserved
16h WORD secondary status
18h BYTE PCI bus number
19h BYTE CardBus bus number
1Ah BYTE subordinate bus number
1Bh BYTE CardBus latency timer
1Ch DWORD memory base address 0
20h DWORD memory limit 0
24h DWORD memory base address 1
28h DWORD memory limit 1
2Ch WORD I/O base address 0
2Eh WORD I/O base address 0 high word (optional)
30h WORD I/O limit 0
32h WORD I/O limit 0 high word (optional)
34h WORD I/O base address 1
36h WORD I/O base address 1 high word (optional)
38h WORD I/O limit 1
3Ah WORD I/O limit 1 high word (optional)
3Ch BYTE interrupt line
3Dh BYTE interrupt pin (read-only) (no interrupt used if 00h)
3Eh WORD bridge control
40h WORD subsystem vendor ID
42h WORD subsystem device ID
44h DWORD 16-bit PC Card legacy mode base address (for accessing ExCa
registers)
48h 14 DWORDs reserved
80h 32 DWORDs varies by device (see #0821,#0822,#0851,#0879)
Bitfields for PCI Configuration Command Register:
Bit(s) Description (Table 0799)
0 I/O access enabled
1 memory access enabled
2 bus master enable
3 special cycle recognition enabled
4 memory write and invalidate enabled
5 VGA palette snoop enabled
6 parity error response enabled
7 wait cycles enabled
8 system error (SERR# line) enabled
9 fast back-to-back transactions enabled
15-10 reserved
See Also: #0798,#0800
Format of PCI Configuration Status Register:
Bit(s) Description (Table 0800)
3-0 reserved (0)
4 new capabilities list is present (first entry pointed at by byte at
34h or 14h)
5 capable of running at 66 MHz
6 UDF supported
7 capable of fast back-to-back transactions
8 data parity error reported
10-9 device select timing
00 fast
01 medium
10 slow
11 reserved
11 signaled target abort
12 received target abort
13 received master abort
14 signaled system error (device is asserting SERR# line)
15 detected parity error (set even if parity error reporting is disabled)
Note: bits 12, 13 and 15 are cleared by writing a 1 into the corresponding
bit
See Also: #0798,#0799
Bitfields for PCI Configuration Built-In Self-Test register:
Bit(s) Description (Table 0801)
3-0 completion code (0000 = successful)
5-4 reserved
6 start BIST (set to one to start, cleared automatically on completion)
7 BIST-capable
Notes: this register is hardwired to 00h if no BIST capability
software should timeout the BIST after two seconds
See Also: #0798
Bitfields for PCI Configuration Base Address:
Bit(s) Description (Table 0802)
0 address type (0 = memory space, 1 = I/O space)
---memory address---
2-1 address type
00 anywhere in first 4GB
01 below 1MB
10 anywhere in 64-bit address space
11 reserved
3 prefetchable
31-4 bits 31-4 of base memory address if addressable in first 1MB or 4GB
63-4 bits 63-4 of base memory address if addressable in 64-bit memory
(bits 63-32 are stored in the following base address DWORD)
---I/O address---
1 reserved
31-2 bits 31-2 of base I/O port
See Also: #0798,#0827
Bitfields for PCI Configuration Expansion ROM Address:
Bit(s) Description (Table 0803)
0 address decode enable (ROM address is valid)
10-1 reserved
31-11 bits 31-11 of ROM's starting physical address
See Also: #0798
Format of PCI Capabilities List:
Offset Size Description (Table 0804)
00h BYTE capability identifier
01h PCI Power Managment
01h BYTE offset of next item (within configuration space) or 00h
N BYTEs varies by capability type
---PCI Power Management---
02h WORD power managment capabilities (see #0805) (read-only)
04h WORD power managment capabilities status register (see #0806)
06h BYTE PMCSR bridge support extensions (see #0807)
07h BYTE (optional) read-only data register (see #0808)
Note: this information is from the v0.93 draft of the specification and is
subject to change
See Also: #0798,#0800
Bitfields for PCI Power Management Capabilities:
Bit(s) Description (Table 0805)
15 reserved (0)
14-12 PME# support
bit 12: PME# can be asserted from power state D0
bit 13: PME# can be asserted from power state D1
bit 14: PME# can be asserted from power state D2
11 reserved (0)
10 D2 power state supported
9 D1 power state supported
8 full-speed clock is required in state D0 for proper operation
(if clear, device may be run at reduced clock except when actually
being accessed)
7-6 dynamic clock control support
00 not bridge, no dynamic clock control, or secondary bus' clock is
is tied to primary bus' clock
01 bridge is capable of dynamic clock control
10 reserved
11 secondary bus has independent clock, but dynamic clock not supported
5 device-specific initialization is required
4-3 reserved (0)
2-0 specification version
001 = v1.0; four bytes of power management registers
Note: this information is from the v0.93 draft of the specification and is
subject to change
See Also: #0804,#0806,#0807
Bitfields for PCI Power Management Capabilities Status Register:
Bit(s) Description (Table 0806)
15 PME status: if set, PME# is (or would be) asserted
writing a 1 to this bit clears it
14-13 (read-only) scale factor to apply to contents of Data register
00 unknown (or unimplemented data)
01 x0.1
10 x0.01
11 x0.001
12-9 (read-write) data select (see #0808)
8 (read-write) enable PME# assertion
7-5 reserved (0)
4 (read-write) enable dynamic data reporting
when set, PME# is asserted whenever the value in the Data register
changes significantly
3-2 reserved (0)
1-0 (read-write) current power state
00 = D0
...
11 = D3
Note: this information is from the v0.93 draft of the specification and is
subject to change
See Also: #0804,#0805,#0807
Bitfields for PCI Power Management PMCSR bridge support extension:
Bit(s) Description (Table 0807)
7 (read-only) Bus Power Control Enable
6 (read-only) Bus Power State B3 supported
5 (read-only) Bus Power State B2 supported
4 dynamic clock control enable
3-0 reserved (0)
Note: this information is from the v0.93 draft of the specification and is
subject to change
See Also: #0804,#0805,#0806
(Table 0808)
Values for PCI Power Management Data Select:
00h D0-state power consumed in watts (+20%/-10%)
01h D1-state power consumed in watts (+20%/-10%)
02h D2-state power consumed in watts (+20%/-10%)
03h D3-state power consumed in watts (+20%/-10%)
04h D0-state power dissipated into chassis in watts
05h D1-state power dissipated into chassis in watts
06h D2-state power dissipated into chassis in watts
07h D3-state power dissipated into chassis in watts
08h-0Fh reserved
See Also: #0806
Bitfields for PCI Configuration CardBus CIS Pointer:
Bit(s) Description (Table 0809)
2-0 address space
000 in device's device-specific configuration space
001 in memory pointed to by base address register 0
...
110 in memory pointed to by base address register 5
111 in device's expansion ROM
27-3 offset within address space defined by bits 2-0
31-28 ROM image number
See Also: #0798
Format of CardBus Socket/ExCA socket interface register space:
Offset Size Description (Table 0810)
00h DWORD Socket Event Register (see #0812)
04h DWORD Socket Mask Register (see #0813)
08h DWORD Socket Present State Register (see #0814)
0Ch DWORD Socket Force Event Register (see #0815)
10h DWORD Socket Control Register (see #0816)
14h 3 DWORDs reserved
20h DWORD Socket Power Management Register
90h BYTE (TI PCI1130) Retry Status Register
91h BYTE (TI PCI1130) Card Control Register (see #0817)
.NG limit reached, continued in next section...