DIV             Division, Unsigned                   Flags: O D I T S Z A P C
                                                            ? - - - ? ? ? ? ?
DIV source

        Logic   AL ← AX / source
                AH ← remainder
             or
                AX ← DX:AX / source
                DX ← remainder
             or
                EAX ← EDX:EAX / source  ; 386+
                EDX ← remainder

    DIV performs an unsigned division. The dividend is implicit; only
    the divisor is given as an operand. The type of the divisor
    determines which registers are used:

        Size   Dividend  Divisor   Quotient  Remainder
        byte      AX      r/m8        AL        AH
        word    DX:AX     r/m16       AX        DX
        dword  EDX:EAX    r/m32       EAX       EDX    ; 386+


    Notes
    If the result is too large to fit in the destination, an INT 0
    (Divide by Zero) is generated, and the quotient and remainder are
    undefined.

    When an Interrupt 0 (Divide by Zero) is generated, the saved CS:IP
    value on the 80286+ points to the instruction that failed (the DIV
    instruction).  On the 8086, however, CS:IP points to the
    instruction following the failed DIV instruction.


    Opcode      Format
    F6 /6       DIV  r/m8
    F7 /6       DIV  r/m16
    F7 /6       DIV  r/m32


    Length and timing
    Operands    Bytes   8088    186     286     386     486     Pentium
    r8           2     80-90     29     14      14      16      17   NP
    r16          2    144-162    38     22      22      24      25   NP
    r32          2       -       -       -      38      40      41   NP
    mem8    2+d(0-2)   86-96+EA  35     17      17      16      17   NP
    mem16   2+d(0-2)  150-168+EA 44     25      25      24      25   NP
    mem32   2+d(0-2)     -       -       -      41      40      41   NP