PSRAD           Packed Shift Right Arithmetic, Doubleword

PSRAD destination, count                             CPU: MMX

        Logic   mm(31..0)  <- SignExtend (mm(31..0)  SAR count)
                mm(63..32) <- SignExtend (mm(63..32) SAR count)

    PSRAD performs a shift-arithmetic-right (SAR) operation on each of
    the two doublewords in the destination operand. The count operand
    determines the number of bits to right-shift. The new high-order
    bits of each doubleword are filled with the initial value of the
    sign bit of the doubleword.
    If the value specified by count is greater than 31 (1Fh), each
    doubleword is filled with the initial value of its sign bit.

    The destination operand is an MMX register. The count operand (source
    operand) can be either an MMX register, a 64-bit memory operand, or
    an immediate 8-bit operand. 


    Opcode      Format
    0F E2 /r    PSRAD mm, mm/m64
    0F 72 /4 ib PSRAD mm, imm8