PSLLW           Packed Shift Left Logical, Word

PSLLW destination, count                             CPU: MMX

        Logic   mm(15..0)  <- mm(15..0)  SHL count
                mm(31..16) <- mm(31..16) SHL count
                mm(47..32) <- mm(47..32) SHL count
                mm(63..48) <- mm(63..48) SHL count

    PSLLW shifts the bits of the first operand to the left by the amount
    of bits specified in the count operand and returns the result to the
    destination register. The empty low-order bits are cleared (set to
    zero).
    If the value specified by the second operand is greater than 15 (0Fh)
    the destination is set to all zeros. 

    The destination operand is an MMX register. The count operand (source
    operand) can be either an MMX register, a 64-bit memory operand, or
    an immediate 8-bit operand.


    Opcode      Format
    0F F1 /r    PSLLW mm, mm/m64
    0F 71 /6 ib PSLLW mm, imm8