Layout b7,b6 Reserved b5 SO Screen off b4 S4 Shift 4 b3 DC Dot clock b2 SL Shift load b1 BW (EGA only) b0 8/9 8/9 dot clocks
- Screen off (bit 5) Turns the screen off along with the picture generating logic. Because no time is spent refreshing the screen, the video processor has direct control of the video memory, which facilitates rapid memory access.
0 : Screen is turned on. 1 : Screen is turned off.
- Shift four (bit 4) (see bit 2) 0 : Load the serializers every character clock cycle. 1 : Load the serializers every fourth character clock cycle.
- Dot clock (bit 3) This is the basic graphics clock for the system and is generated from the master clock output. High resolution graphics are achieved when the dot clock is triggered every input clock, but if the dot clock is triggered by the master clock divided by two, then this slows down the system and stretches out the other timing signals. This divide-by-two mode is used to generate the 320 and 360 horizontal resolutions on the VGA, and can also be used to force non-standard VGA modes.
0 : Set the dot clock to the same frequency as the master clock. 1 : Divide the master clock by 2 to derive the dot clock (used in some 320- or 360-column modes).
- Shift load (bit 2) The display memory is organized in parallel words. The display output, however, requires a serial output stream. A device called a video serializer converts this parallel data.
b4 b2 Load serializers 0 0 every char. clock cycle 0 1 every other char. clock cycle 1 ? every fourth char. clock cycle
- 8/9 dot clocks (bit 0) 0 : Character clocks 8 dots wide are generated. Used in all modes in which there are 320 or 640 horizontal dots. 1 : Character clocks 9 dots wide are generated. Used in the monochrome mode 7 in which there are 720 horizontal dots.