A multi-function register that assists in the control of the display. This register can generally be left alone by the programmer (updated by BIOS after mode sets).
- Hardware reset (bit 7) 0 : Places all horizontal and vertical control timings into a control state, thereby forcing a reset condition. 1 : Enables the occurrence of the horizontal and vertical control signals.
- Word/Byte mode (bit 6) Controls the way the internal addresses generated are output to the display memory address bus. Word mode is used in CGA emulation.
- Address wrap (bit 5) Determines whether bit 13 or bit 15 should be output on the least significant address line to the display memory when the system is in a word mode, as indicated in the W/B field in this register.
- Count by two (bit 3) Determines whether the VGA memory address counter is clocked every character clock or every other character clock. This creates either a byte or a word refresh address for the display buffer. It determines the actual difference in conjunction with the Offset register.
0 : The memory address counter is clocked with the character clock input. 1 : The memory address counter is clocked with every other character clock input.
- Horizontal retrace select (bit 2) 0 : Clock the scan-line counter with every horizontal retrace. 1 : Clock the scan-line counter with every horizontal retrace divided by two.
- Select row scan counter (bit 1) 0 : Row scan counter bit 1 is placed on the memory bus bit 14 during active display time. Bit 1, placed on memory address bit 14, has the effect of quartering the memory. 1 : Memory addresses are output sequentially.
- Compatibility mode support (bit 0) 0 : Substitutes row scan address bit 0 for memory address bit 13, causing the memory of the VGA during the graphics modes to be compatible with the CGA's 6845 controller chip.