Format of ET4000/W32 memory-mapped registers
Offset Size Description (Table M057)
00h DWORD MMU Registers: memory base pointer register 0 (see #M058)
04h DWORD MMU Registers: memory base pointer register 1 (see #M058)
08h DWORD MMU Registers: memory base pointer register 2 (see #M058)
0Ch 7 BYTEs ???
13h BYTE MMU Registers: MMU control register (see #M059)
14h 28 BYTEs ???
30h BYTE Non-Queued Registers: suspend/terminate
31h BYTE Non-Queued Registers: operation state (see #M060) (write-only)
32h BYTE Non-Queued Registers: sync enable
33h BYTE ???
34h BYTE Non-Queued Registers: interrupt mask
35h BYTE Non-Queued Registers: interrupt status
36h BYTE Non-Queued Registers: ACL status (read-only)
bit 1: read status (RDST) 1=ACL active, queue not empty
bit 0: write status (WRST) 1=queue full
37h 73 BYTEs ???
80h DWORD Queued Registers: pattern address (see #M061)
84h DWORD Queued Registers: source address (see #M061)
88h WORD Queued Registers: pattern Y offset (see #M062)
8Ah WORD Queued Registers: source Y offset (see #M062)
8Ch WORD Queued Registers: destination y offset (see #M062)
8Eh BYTE Queued Registers: virtual bus size
8Fh BYTE Queued Registers: X/Y direction (see #M063)
90h BYTE Queued Registers: pattern wrap (see #M064)
91h BYTE ???
92h BYTE Queued Registers: source wrap (see #M064)
93h BYTE ???
94h WORD Queued Registers: X position
96h WORD Queued Registers: Y position
98h WORD Queued Registers: X count (see #M065)
9Ah WORD Queued Registers: Y count (see #M065)
9Ch BYTE Queued Registers: routine control (see #M066)
9Dh BYTE Queued Registers: reload control
9Eh BYTE Queued Registers: background ROP for mixing
9Fh BYTE Queued Registers: foreground ROP for mixing
A0h DWORD Queued Registers: destination address
A4h DWORD Queued Registers: internal pattern address
A8h DWORD Queued Registers: internal source address
Bitfields for ET4000/W32 memory base pointer register:
Bit(s) Description (Table M058)
31-22 reserved
21-0 memory base pointer
See Also: #M057
Bitfields for ET4000/W32 MMU control register:
Bit(s) Description (Table M059)
7 reserved
6-4 linear address control (LAC)
bit 6: MMU aperture 2
bit 5: MMU aperture 1
bit 4: MMU aperture 0
3 reserved
t2-0 aperture type (APT)
bit 2: MMU aperture 2
bit 1: MMU aperture 1
bit 0: MMU aperture 0
See Also: #M057
Bitfields for ET4000/W32 operation state register:
Bit(s) Description (Table M060)
7-4 reserved
3 restart operation after ACL-interruption
2-1 reserved
0 restore status before ACL-interruption
See Also: #M057
Bitfields for ET4000/W32 memory address register:
Bit(s) Description (Table M061)
31-22 reserved
21-0 memory base pointer
See Also: #M057
Bitfields for ET4000/W32 offset register:
Bit(s) Description (Table M062)
15-12 reserved
11-0 Y offset
See Also: #M057
Bitfields for ET4000/W32 X/Y direction register:
Bit(s) Description (Table M063)
7-2 reserved
1 X direction
0 Y direction
See Also: #M057
Bitfields for ET4000/W32 wrap register:
Bit(s) Description (Table M064)
7 reserved
6-4 pattern Y wrap
000 = 1 line
001 = 2 lines
010 = 4 lines
011 = 8 lines
100 = reserved
101 = reserved
110 = reserved
111 = no wrap
3 reserved
2-0 pattern X wrap
000 = reserved
001 = reserved
010 = 4 byte
011 = 8 byte
100 = 16 byte
101 = 32 byte
110 = 64 byte
111 = no wrap
See Also: #M057
Bitfields for ET4000/W32 count register:
Bit(s) Description (Table M065)
15-12 reserved
11-0 pixel count
See Also: #M057
Bitfields for ET4000/W32 routine control register:
Bit(s) Description (Table M066)
7-6 reserved
5-4 routing of CPU address (ADRO)
00 don't use CPU address
01 CPU address is destination
10 reserved
11 reserved
3 reserved
2-0 routing of CPU data (DARQ)
000 don't use CPU data
001 CPU data is source data
010 CPU data is mixed data
011 reserved
100 CPU data is x-count
101 CPU data is y-count
10x reserved
See Also: #M057
--------V-MC0000000--------------------------
MEM C000h:0000h - VIDEO BIOS (EGA and newer)
Size: varies (usually 16K-24K for EGA, 24K-32K for VGA)
--------h-mC0000000--------------------------
MEM C0000000h - Weitek "Abacus" math coprocessor
Size: 4096 BYTEs
--------B-MC8000000--------------------------
MEM C800h:0000h - HARD DISK BIOS
Size: varies (usually 8K or 16K)
--------V-MC8001C00--------------------------
MEM C800h:1C00h - IBM XGA, XGA/A - MEMORY-MAPPED REGISTERS
Range: any 8K boundary within segments C000h to DFFFh
Notes: The XGA memory mapped registers can be assigned to the last 1K block in
in each 8K block in the range of C0000h-DFFFFh; the base offset of
the 128 memory mapped lcoation for a particular XGA instance is
Segment:(1C00h+instance*80h) for each XGA installed in a system
(default instance is 6). The instance number may be read from the
XGA's Programmable Option Select registers
The XGA/A (PS/2 adapter) uses the 7KB area below the memory-mapped
register area for ROM data; the XGA (PS/2 onboard) has included
this area in it's video BIOS ROM.
Most of the memory mapped registers are from the graphics coprocessor,
while the I/O-registers are for the display controller.
--------A-MF0006000--------------------------
MEM F000h:6000h - IBM PC ROM BASIC
Size: 32768 BYTEs
--------B-MF000E000--------------------------
MEM F000h:E000h - ORIGINAL IBM PC ROM BIOS
Size: 8192 BYTEs
--------H-MF000FFF0--------------------------
MEM F000h:FFF0h - RESET JUMP
Size: 5 BYTEs
--------B-MF000FFF5--------------------------
MEM F000h:FFF5h - ASCII BIOS DATE
Size: 8 BYTEs
--------B-MF000FFFD--------------------------
MEM F000h:FFFDh - OFTEN USED TO ENSURE CORRECT BIOS CHECKSUM
Size: BYTE
--------B-MF000FFFE--------------------------
MEM F000h:FFFEh - MACHINE TYPE CODE
Size: BYTE
See Also: INT 15/AH=C0h
--------B-MF000xxxx--------------------------
MEM F000h:xxxxh - AWARD Flash Hook