Format of S3 Local Peripheral Bus memory-mapped registers
Offset Size Description (Table M095)
FF00h DWORD "mode" various bit flags (see #M096)
FF04h DWORD FIFO status
(bits 3-0 = 1000 when ready for data access via FF40h)
FF08h DWORD interrupt status
bit 1: IRQ disable? (also see S3 CR32 bit 4)
bit 2: card is asserting IRQ (write 1 to clear)
bit 17: ? (also related to S3 CR32 bit 4)
bit 18: ? (also related to S3 CR32 bit 4)
FF0Ch DWORD frame buffer address 0
offset within frame buffer at which to store incoming data from
LPB
(read by RFM_GETVIDEOATTRIBUTES function 0066h)
FF10h DWORD frame buffer address 1
(W95 drivers copy this into 81D4h when unfreezing video)
FF14h DWORD "direct address" = index for FF18h (see #M099)
FF18h DWORD "direct data" (see #M099)
FF1Ch DWORD general purpose I/O
bits 3-0: ???
bits 7-4: ??? (read-only?)
bits 31-8: unused? (read-only 0)
FF20h DWORD "serial port" -- I2C access (see #M098)
FF24h DWORD input window size (high word = rows, low word = columns)
FF28h DWORD data offsets
(video alignment; high word = rows ; low word = columns)
FF2Ch DWORD horizontal decimation
bits 0-31 set indicate that pixels [bytes???] 0-31 (mod 32)
of each line should be dropped
FF30h DWORD vertical decimation
bits 0-31 set indicate that lines 0-31 (mod 32) should be
dropped, i.e. setting this DWORD to 55555555h will drop
every other line
FF34h DWORD line stride (number of bytes between starts of successive lines
of video data)
must be multiple of 4 -- lowest two bits forced to 0
FF38h 3 DWORDs unused??? (seem to echo FF34h)
FF40h DWORD "output FIFO" - data transfer
on ISA bus, there must be a delay between successive writes
FF44h 7 DWORDs unused??? (seem to echo FF40h)
See Also: #M097
Bitfields for S3 Local Peripheral Bus "Mode" register:
Bit(s) Description (Table M096)
0 ??? (Win95 drivers clear at startup)
2-1 ??? (Win95 drivers clear at startup)
3 ??? (Win95 drivers set at startup)
4 ??? (Win95 drivers pulse this bit at times)
5 freezes video image when set
6 (switches colors to magenta/green) (refer to bit 26 below)
9-7 ???
10 ??? messes up video image when set
15-11 read-only???
16 ???
17 ???
19-18 read-only???
20 read-only???
21 ???
22 ???
23 read-only???
24 ??? (if =0, colors are messed up, and horizontal jitter added)
25 ???
26 ??? (switches colors to magenta/green)
bits 26&6:
00 magenta/green
01 (default) normal
10 internal byte-swapping???
11 magenta/green
27 ???
28 current odd/even video field status
29 field inversion - when set, the LPB's FIELD pin state is inverted
before being reported in bit 28
31-30 ??? (read-only 0)
Note: RFM_OPEN sets this register to 00200049h
See Also: #M095
(Table M099)
Values for S3 Local Peripheral Bus "direct address" index:
0000h CP3 installation (FF18h reads 00C3h if installed)
0001h ?
0002h ?
0003h ?
bit 7: ???
bits 6-0: ???
0004h ?
0005h ?
bits 7-0: ???
0020h ?
0028h ?
0034h ?
0500h ?
0504h ?
0508h ?
050Ch ?
0510h ?
See Also: #M095
Bitfields for S3 Local Peripheral Bus serial-port register:
Bit(s) Description (Table M098)
0 I2C clock line [SCL] (write)
1 I2C data line [SDA] (write)
2 I2C clock line (read)
3 I2C data line (read)
4 enable I2C interface?
31-5 ???
Note: see file I2C.LST for details of the I2C device registers accessible
through this interface
See Also: #M095
--------V-MB0000000--------------------------
MEM B000h:0000h - MDA TEXT BUFFER
Size: 4096 BYTEs
--------V-MB0000000--------------------------
MEM B000h:0000h - HGC+ RAMFont-MODE TEXT BUFFER
Size: 16384 BYTEs
Note: in RAMFont Mode 1, the memory is filled with the usual
character/attribute pairs; in RAMFont Mode 2, four bits of each
'attribute' byte is used to provide 12 bits for specifying the
character
--------V-MB0000000--------------------------
MEM B000h:0000h - HGC GRAPHICS BUFFER (PAGE 0)
Size: 32768 BYTEs
--------V-MB4000000--------------------------
MEM B400h:0000h - HGC+ RAMFont BUFFER
Size: 4096 BYTEs
Notes: apparently write-only
RAMFont Mode 1: 256 characters (8 bits each for char and attribute)
RAMFont Mode 2: 3072 characters (12 bits for char, 4 bits for attrib)
each character definition is 8 pixels wide (with 9th-column duplication
if appropriate) by 8-16 pixels high
--------V-MB8000000--------------------------
MEM B800h:0000h - CGA TEXT/GRAPHICS BUFFER
Size: 16384 BYTEs
--------V-MB8000000--------------------------
MEM B800h:0000h - EGA/VGA+ TEXT BUFFER
Size: 32768 BYTEs
--------V-MB8000000--------------------------
MEM B800h:0000h - HGC GRAPHICS BUFFER (PAGE 1)
Size: 32768 BYTEs
--------V-MBFF00000--------------------------
MEM BFF0h:0000h - ET4000/W32 ACL accelerator
Size: 169 BYTES