Format of S3 memory-maped port control registers

Offset  Size    Description     (Table M101)
8200h  DWORD   FIFO control
8204h  DWORD   MIU control
8208h  DWORD   streams timeout
820Ch  DWORD   miscellaneous timeout
8210h 4 DWORDs ???
8220h  DWORD   DMA read base address
8224h  DWORD   DMA read stride width

See Also: #M100
--------V-MA00082E8--------------------------
MEM A000h:82E8h - S3 - MEMORY-MAPPED CURRENT Y POSITION REGISTER
Size:  WORD

Note:  the S3 graphics processor registers can be mapped at either
     linear 000A0000h or at offset 16M from the start of the linear
     frame buffer

See Also: PORT 82E8h
--------V-MA00083B0--------------------------
MEM A000h:83B0h - S3 - MEMORY-MAPPED VGA REGISTERS
Size:  48 BYTEs

Note:  the S3 graphics processor registers can be mapped at either
     linear 000A0000h or at offset 16M from the start of the linear
     frame buffer
--------V-MA0008504--------------------------
MEM A000h:8504h - S3 - MEMORY-MAPPED SUBSYSTEM REGISTERS
Size:  12 BYTEs

Note:  the S3 graphics processor registers can be mapped at either
     linear 000A0000h or at offset 16M from the start of the linear
     frame buffer