00B - Status Register B
Real Time Clock Status Register.
1xxx xxxx Set
When set to 0, this bit updates the cycle,
normally by advancing the counts at a rate of
one per second. When set to 1, this bit
immediately ends any update cycle in progress,
and the program can initialize the 14 time bytes
without any futher updates occurring until this
bit is set to 0.
x1xx xxxx Periodic Interrupt Enable
This bit is a read/write bit that allows an
interrupt to occur at a rate specified by the
rate and divider bits in Status Register A
(00A). When set to 1, this bit enables inter-
rupt. The system initializes this bit to 0.
xx1x xxxx Alarm Interrupt Enable
When set to 1, this bit enables the alarm inter-
rupt. The system initializes this bit to 0.
xxx1 xxxx Update-Ended Interrupt Enabled
When set to 1, this bit enables the update-
ended interrupt. The system initializes
this bit to 0.
xxxx 1xxx Square Wave Enabled
When set to 1, this bit enables the square-
frequency as set by the rate-selection bits
in Status Register A (00A). The system initia-
lizes this bit to 0.
xxxx x1xx Date Mode
This bit indicates if the time-and-date calendar
updates use binary or binary-coded-decimal (BCD)
formats. When set to 1, this bit indicates a
binary format. The system initializes this bit
to 0.
xxxx xx1x 24-Hour Mode
This bit establishes if the hours byte is in
the 24-hour or 12-hour mode. When set to 1, this
bit indicates the 24-hour mode. The system
initializes this bit to 1.
xxxx xxx1 Daylight Savings Enabled
When set to 1, this bit enables the daylight
savings time mode. When set to 0, it disables
the mode, and the clock reverts to standart
time. The system initializes this bit to 0.