00A - Status Register A

        Real Time Clock Status Register.

                1xxx xxxx  Update in Progress
                             When set to 1, this bit indicates the time-
                             update cycle is in progress. When set to 0,
                             it indicates the current date and time can
                             be read.
                x111 xxxx  22-Stage Divider
                             These three divider-selection bits identify
                             which time-base frequency is being used. The
                             system initializes these bits
                             to binary 010, which selects a 32.768 kHz
                             time base. This value is the only value
                             supported for proper time-keeping.
                xxxx 1111  These bits allow the selection of a divider
                             output frequency. The system initializes these
                             bits to a binary 0110, which selects a 1.024 kHz
                             square-wave output frequency and a 976.562 ms
                             periodic interrupt rate.