LGDT Load Global Descriptor Table Reg. Flags: Not altered LIDT Load Interrupt Descriptor Table Reg.
LGDT source CPU: 286+ Priv LIDT source CPU: 286+ Priv
Logic GDTR ← base:limit or IDTR ← base:limit
The LGDT and LIDT instructions load a limit value and linear base address from a six-byte (48-bit) data operand in memory (pseudo-descriptor) into the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR), respectively. The 16-bit limit is stored at the low word and the 32-bit base at the high doubleword of the operand.
If a 16-bit operand-size attribute is used with LGDT or LIDT, the register is loaded with a 16-bit limit and a 24-bit base (80286), and the high-order 8 bits of the 48-bit operand are not used. If a 32-bit operand-size attribute is used, the register is loaded with a 16-bit limit and a 32-bit base (80386+); the high-order 8 bits of the 48-bit operand are used as high-order base address bits.
The SGDT and SIDT instructions always store all 48 bits of the data operand. With the 80286, the upper 8 bits are undefined after SGDT or SIDT is executed. With the 80386+, the upper 8 bits are written with the high-order 8 address bits, for both a 16-bit and a 32-bit operand-size attribute. If LGDT or LIDT are used with a 16-bit operand to load the register stored by SGDT or SIDT, the upper 8 bits are stored as zeros.
LIDT tells the hardware where to go in case of interrupts.
LGDT and LIDT appear in operating system software; they are not used in application programs. They are the only instructions that directly load a linear address (i.e. not a segment relative address) in protected mode.
Opcode Format 0F 01 /2 LGDT m16&32 0F 01 /3 LIDT m16&32