PSRLD           Packed Shift Right Logical, Doubleword

PSRLD destination, count                             CPU: MMX

        Logic   mm(31..0)  <- mm(31..0)  SHR count
                mm(63..32) <- mm(63..32) SHR count
    
    PSRLD performs a shift-logical-right operation on each of the two
    doublewords in the destination operand. The count operand determines
    how many bits to right-shift. The new high-order bits are cleared
    (set to zero).
    If the value specified by the count operand is greater than 31 (1Fh)
    the destination is set to all zeros.

    The destination operand is an MMX register. The count operand (source
    operand) can be either an MMX register, a 64-bit memory operand, or
    an immediate 8-bit operand.


    Opcode      Format
    0F D2 /r    PSRLD mm, mm/m64
    0F 72 /2 ib PSRLD mm, imm8