PMULLW          Packed Multiply Low on Words

PMULLW destination, source                           CPU: MMX

        Logic   
        mm(15..0)  <- ( mm(15..0)  * mm/m64(15..0)  ) AND 0FFFFh
        mm(31..16) <- ( mm(31..16) * mm/m64(31..16) ) AND 0FFFFh
        mm(47..32) <- ( mm(47..32) * mm/m64(47..32) ) AND 0FFFFh
        mm(63..48) <- ( mm(63..48) * mm/m64(63..48) ) AND 0FFFFh

    The PMULLW instruction multiplies the four signed or unsigned words
    of the destination operand with the four signed or unsigned words of
    the source operand. The low-order 16 bits of the 32-bit intermediate
    results are written to the destination operand. 

    The destination operand is an MMX register. The source operand can
    either be an MMX register or a 64-bit memory operand.


    Opcode      Format
    0F D5 /r    PMULLW mm, mm/m64