PMADDWD         Packed Multiply and Add

PMADDWD destination, source                          CPU: MMX

        Logic
        mm(31..0)  <- mm(15..0) *mm/m64(15..0)  + mm(31..16)*mm/m64(31..16)
        mm(63..32) <- mm(47..32)*mm/m64(47..32) + mm(63..48)*mm/m64(63..48)

    The PMADDWD instruction multiplies the four signed words of the
    destination operand by the four signed words of the source operand.
    The result is two 32-bit doublewords. The two high-order words are
    summed and stored in the upper doubleword of the destination operand.
    The two low-order words are summed and stored in the lower doubleword
    of the destination operand. This result is written to the destination
    operand. 

    The destination operand is an MMX register. The source operand can
    either be an MMX register or a 64-bit memory operand.

    The PMADDWD instruction wraps around to 80000000h only when all four
    words of both the source and destination operands are 8000h.


    Opcode      Format
    0F F5 /r    PMADDWD mm, mm/m64