PANDN           Bitwise AND NOT

PANDN destination, source                            CPU: MMX

        Logic   destination <- (NOT destination) AND source

    PANDN performs a bitwise logical NOT on the 64 bits of the
    destination operand. The NOT inverts each of the 64 bits of the
    destination register so that every 1 becomes a 0, and visa versa. 
    The instruction then performs a bitwise logical AND on the inverted
    64 bits of the destination operand and on the source operand. Each
    bit of the result of the AND instruction is set to 1 if the
    corresponding bits are 1. Otherwise, it is set to 0. The result is
    written to the destination register. 

    The destination operand is an MMX register. The source operand can
    either be an MMX register or a 64-bit memory operand


    Opcode      Format
    0F DF /r    PANDN mm/m64