FPU registers
The FPU has 13 registers: 8 data registers, a control register,
a status register, a tag register, an instruction pointer, and
a data pointer.
79 64 Data registers 0 1 0
R7 ┌─┬────────┬───────────────────────────────────────┐ ┌───┐
R6 ├─┼────────┼───────────────────────────────────────┤ ├───┤
R5 ├─┼────────┼───────────────────────────────────────┤ ├───┤
R4 ├─┼────────┼───────────────────────────────────────┤ ├───┤
R3 ├─┼────────┼───────────────────────────────────────┤ ├───┤
R2 ├─┼────────┼───────────────────────────────────────┤ ├───┤
R1 ├─┼────────┼───────────────────────────────────────┤ ├───┤
R0 ├─┼────────┼───────────────────────────────────────┤ ├───┤
└─┴────────┴───────────────────────────────────────┛ └───┛
bit 79 sign ▲
bits 78..64 exponent │
bits 63..0 significand 15 0 │
┌─────────────┐ │
│ Control reg │ │
┌─────────────────────────────┐ ├─────────────┤ │
│ Instruction pointer │ │ Status reg │ │
├─────────────────────────────┤ ├─────────────┤ │
│ Data pointer │ │ Tag word │ ◄─┛
└─────────────────────────────┛ └─────────────┛
The FPU register stack
Some FPU instructions operate on the data registers explicitly,
others access the registers as a stack. Those instructions
operate on the top one or two stack elements. Here, the TOP
field in the FPU status word identifies the current top-of-stack
register. A push operation decrements TOP by one and loads a
value into the new top register. A pop operation stores the
value from the current top register and increments TOP by one.
Like other x86 stacks, the FPU register stack grows downward,
toward lower-numbered registers.
Some FPU instructions address the data registers implicitly,
while others address them explicitly. Many instructions operate
on the register at the top of the stack by implicitly addressing
the register at which TOP points. Other instructions let the
programmer specify which register to use, relative to TOP,
using the ST(i) notation.
Status word
The status word reflects the overall state of the FPU.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
┌───┬───┬───────────┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┐
│ B │ C3│ TOP │ C2│ C1│ C0│ ES│ S │ P │ U │ O │ Z │ D │ I │
└───┴───┴───────────┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┛
B busy; reflects the contents of the ES field
(for 8087 compatibility)
TOP register number of the top of stack
C3..C0 condition codes
ES error status, holds the logical OR of bits 0..5
(a.k.a. IR field -- interrupt request pending)
Exception flags:
S stack over/underflow (387+)
P precision lost
U underflow
O overflow
Z zero-divide
D denormalization
I invalid operation (e.g. stack overflow)
Control word
The contents of the control word determine the FPU's mode of
operation.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
┌───┬───┬───┬───┬───────┬───────┬───┬───┬───┬───┬───┬───┬───┬───┐
│ │ │ │ IN│ RC │ PC │ IE│ │ P │ U │ O │ Z │ D │ I │
└───┴───┴───┴───┴───────┴───────┴───┴───┴───┴───┴───┴───┴───┴───┛
IN infinity (8087 and 80287 only)
RC rounding control (default is 00)
00 to nearest or even
01 round down
10 round up
11 truncate (chop)
PC mantissa precision control
00 24 bits
01 reserved
10 53 bits
11 64 bits
IE FPU interrupt enable (active on 8087 only)
5..0 Exception masks (if set, condition is ignored)
Tag word
The 16-bit tag word contains 8 two-bit tags where each tag
reports on the content of an FPU data register. Primarily, the
tag word optimizes the FPU's performance and stack handling by
making it possible to distinguish between empty and non-empty
register locations. It also enables exception handlers to check
the contents of a stack location without having to decode the
actual data.
15 0
┌───────┬───────┬───────┬───────┬───────┬───────┬───────┬───────┐
│ Tag(7)│ Tag(6)│ Tag(5)│ Tag(4)│ Tag(3)│ Tag(2)│ Tag(1)│ Tag(0)│
└───────┴───────┴───────┴───────┴───────┴───────┴───────┴───────┛
A tag can have the following values:
00 valid
01 zero
10 QNaN, SNaN, infinity, denormal and unsupported formats
11 empty
Instruction and data pointers
Because the FPU operates in parallel with the CPU's ALU
(arithmetic and logic unit), an error the FPU detects may be
reported after the ALU executes the instruction that caused the
error. To allow a failing numeric instruction to be identified,
the FPU contains two pointer registers that supply the address
of the failing instruction and (if appropriate) the address of
its numeric operand.
Refer to Intel's documentation for details, esp. for pre-387
FPUs.