Vert retrace end       index 11h  CRTC    (protected)

Layout  b7     PR   Protect CRTC registers 0 to 7
        b6     BW   Bandwidth (refresh cycle select)
        b5     DVI  (EGA only)
        b4     CVI  (EGA only)
        b4-b0  EVR  Vertical retrace end (4 or 5 bits??)

        Note
        This register is protected by the CR field in the End
        horizontal blanking register.

- Protect CRTC registers 0-7 (bit 7)
        Protects the CRTC registers at indexes 0 to 7 from being
        modified. The lower 8 registers in the CRTC contain sensitive
        horizontal and vertical timing settings. Software expecting
        the EGA may program these registers unwittingly.

        0 : No protection is active.
        1 : Writing from the host to CRTC registers 0-7 is disabled.

- Vertical retrace end (bits 4-0 (3-0??))
        The low-order 5 (4??) bits of the value that will cause the
        vertical retrace period to end. The horizontal scan line count
        is compared to the Vertical retrace start register. When the
        values are equal, a vertical retrace period is started. After
        this time, the low-order five bits of the scan line counter
        are compared to the five bits in the EVR field. When they are
        equal, the vertical retrace period ends.