- Chain four (bit 3) Controls the manner in which the display memory bit planes are accessed. - In a write mode, the display bit plane is normally selected by the EM0-EM3 enable memory mask fields of the Map mask register. Any combination of the four display planes may be accessed simultaneously. In mode 13h, the four display planes are chained together, and only one can be selected at a time. In this mode, the two low-order address bits are used to select which of the four display planes are enabled. Thus, four sequential bytes written to the display memory are stored so that one byte occupies an identical addressed location in each of the 4 display planes. - In a read mode, only one display memory bit plane can be active at a time. The active bit plane is normally selected by the read map select (RMS) field of the Read map register. In mode 13h, the operation is identical to the write operation above, with the Read map select register being ignored and the display plane being selected by the low-order A1 and A0 address bits.
0 : The display planes are selected via the Map mask and the Read map select registers. 1 : The display planes are selected by the low-order A1 and A0 address bits; the four display planes are assumed to be chained.
- Odd/even (bit 2) Determines whether the processor addresses a display memory plane sequentially, or whether odd addresses access planes 1 and 3 and even addresses access display planes 0 and 2.
Note that the value of this bit should be the complement of the value in the OE field of the Mode register.
0 : Enables the odd/even addressing mode. 1 : Directs the system to use a sequential addressing mode.