A: supports the CPUID instruction and
executing function 1 (EAX=1) with CPUID.
WRMSR writes to a Model Specific Register. EDX:EAX contain the value to
write into the register whose number is given in ECX.
RDMSR reads from a Model Specific Register. EDX:EAX will receive the value
from the MSR whose number is given in ECX.
List of Model Specific Registers:
00h Machine Check Exception-Address register (Read-only)
01h Machine Check Exception-Type register (Read-only)
02h Unknown
..
0dh Unknown
0eh Test register T12
0fh Unknown
10h Time Stamp Counter (See RDTSC)
11h Counter / Event Selection register (See CESR Map)
12h Counter #0 (40 bit resolution)
13h Counter #1 (40 bit resolution)
CESR Map. Note that CESR is a 64-bit register, of which only the
bottom 32 bits are currently known to be used.
Bit 31 16 0
┌─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬┴┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┐
│r│r│r│r│r│r│r│c│3│2│t│t│t│t│t│t│r│r│r│r│r│r│r│C│3│2│T│T│T│T│T│T│
└─┴─┴─┴─┴─┴─┴─┴┼┴┼┴┼┴┼┴─┴─┴─┴─┴┼┴─┴─┴─┴─┴─┴─┴─┴┼┴┼┴┼┴┼┴─┴─┴─┴─┴┼┛
│ │ │ └─────┬───┛ │ │ │ └────┬────┛
Counting method┛ │ └─────┐ │ ──────────────────┛ │ │ │
Allow counting in CPL3 │ │ ────────────────────┛ │ │
Allow counting in CPL0-2─┛ │ ──────────────────────┛ │
Event type (what to count)─┛ ─────────────────────────────┛
(see list below)
└──────────┬──────────────────┛ └────────────┬────────────────┛
Counter #1:─┛ Counter #0:─┛
Counting methods: 1= count CPU cycles 0= count events
Allow count in CPL3: 1= Yes 0= No
Allow count in CPL0-2: 1= Yes 0= No
Event Type List:
00h data read
01h data write
02h data TLB miss
03h data read miss
04h data write miss
05h Write (hit) to M (modified) or E (exclusive) cacheline
(MESI protocol)
06h data cache lines written back
07h data cache snoops
08h data cache snoop hits
09h memory accesses in both pipes
(cumulative ?)
0ah data bank access conflicts (U & V pipe access same data line in
data cache).
0bh misaligned data memory references
0ch code read
0dh code TLB miss
0eh code cache miss
0fh any segment register load
10h segment descriptor cache accesses
11h segment descriptor cache hits
12h branches
13h Branch Target Buffer (BTB) hits
14h taken branch or BTB hit
15h pipeline flushes
16h instructions executed
17h instructions executed in V pipe
18h bus utilization (apparently events in which the CPU has to wait
for bus access).
19h pipeline stalled by write backups
1ah pipeline stalled by data memory read
1bh pipeline stalled by write to M or E line
1ch locked bus cycle (for instance during xchg)
1dh I/O read or write cycles
1eh noncacheable memory references
1fh pipeline stalled by Address Generation Interlock (AGI)
20h unknown
21h unknown
22h floating point operations
23h breakpoint 0 match
24h breakpoint 1 match
25h breakpoint 2 match
26h breakpoint 3 match
27h hardware interrupts
28h data read or data write
29h data read miss or data write miss
(All info provided by Christian Ludloff)
All mentioned x86 CPU instructions by Mnemonic
──────────────────────────────────────────────────────────────────────────────
Click on any instruction mnemonic to see details.
See <Breakpoint errors> for CPU bugs relating to debugging.
See <Chip Step info> for a summary on revision codes.
See <General FPU bugs> for FPU bugs unrelated to instructions.
See <FPU mnemonics> for FPU bugs related to FPU instructions.
See <List of NEC mnemonics> for a list of NEC instructions.
See <NEC general info> for a summary of special features in NECs.
<AAA> Adjust after addition <AAD> Adjust after division
<AAM> Adjust after multiply <AAS> Adjust after subtraction
<BOUND> Bounds check
<BSF> Bit scan forward <BSWAP> 4-Byte swap (e-registers)
<BT> Bit test <BTC> Bit test & complement
<BTR> Bit test & reset <BTS> Bit test & set
<CHKIND> Alias mnemonic for BOUND on NEC
<CMPS> CMPSB CMPSW CMPSD String compare, Byte, Word, Doubleword
<CMPXCHG> Compare & exchange <CPUID> Identify CPU (486+)
<CR0> CR1 CR2 CR3 CR4 Map of control registers
<EFLAGS> Map of EFLAGS register
<HLT> Halt the CPU <IBTS> Insert bit string
<IMUL> Integer multiply
<INS> INSB INSW INSD Input of string from I/O port, Byte, Word, Doubleword
<INVD> Invalidate cache <JMP> Unconditional jump
<LAR> Load access rights <LOADALL> Load all registers.
<LSL> Load segment limit <MOV> Move data to/from registers
<MOVS> Move string <MUL> Multiply unsigned
<POP> Pop data from stack <POPA> Pop all registers
<PUSH> Push value onto stack <RDTSC> Read time stamp counter
<RDMSR> Read Model Specific Register (Pentium+)
<Rotate and Shift> Concerns all Rotation and Shift instructions
<SETALC> Carry bit to all of al <UNKNOWN> An unknown opcode
<VERR> Verify segment for Read <VERW> Verify segment for Write
<WBINVD> Write Back and Invalidate Cache (486+)
<WRMSR> Write Model Specific Register (Pentium+)
All mentioned FPU instructions by Mnemonic
──────────────────────────────────────────────────────────────────────────────
Alphabetic listing on FPU Mnemonics for instructions behaving different
than expected. Instructions marked with * are considered undocumented.
* <FCOS> FPU Cosine in radians on IIT math coprocessor
<FDISI / FNDISI> Disable Floating point interrupts
<FDIV / FDIVP> Divide
<FDIVR / FDIVRP> Divide reversed
<FENI / FNENI> Enable Floating point interrupts
<FLDENV> Load Floating point Environment
<FMUL4X4> Matrix multiply on IIT math coprocessor
<FPREM> Modulus of ST by ST(1) into ST
<FPTAN> Tangent ratio of ST into ST & ST(1)
<FRSTPM> Tells the FPU to use Real (or V86) Mode formats
<FRSTOR> Loads the FPU state from memory see FSAVE
<FSAVE> Saves the FPU state to memory see FRSTOR
* <FSBP0,1,2,3> Bankswitching on IIT math coprocessor
<FSCALE> Adds the value in ST to the exponent in ST(1)
<FSETPM> Tells the FPU to use Protected Mode formats
* <FSIN> FPU Sine in radians on IIT math coprocessor
<FSINCOS> calculates FPU sine and cosine in radians
<FSTENV> Store Floating point Environment
General Intel FPU bugs, unrelated to opcodes
──────────────────────────────────────────────────────────────────────────────