Function:
Loads virtually all processor registers with defined values from memory.
Initialises processor to specified state. Apparently aliased on the 286 by
opcode 0f 04.
The 286 LOADALL instruction reads a block of 102 bytes into the chip,
starting at address 000800 hex.
Memory description for LOADALL read area on 286:
(addresses are in hexadecimal, lengths in decimal)
0800: 6 N/A
0806: 2 MSW (Machine Status Word)
0808: 14 N/A
0816: 2 TR (Task Register)
0818: 2 FLAGS (286 Flags)
081a: 2 IP (Instruction Pointer)
081c: 2 LDT (Local Descriptortable)
081e: 2 DS (Data Segment)
0820: 2 SS (Stack Segment)
0822: 2 CS (Code Segment)
0824: 2 ES (Extra Segment)
0826: 2 DI (Destination Index)
0828: 2 SI (Source Index)
082a: 2 BP (Base Pointer)
082c: 2 SP (Stack Pointer)
082e: 2 BX (BX register)
0830: 2 DX (DX register)
0832: 2 CX (CX register)
0834: 2 AX (AX register)
0836: 6 ES cache (ES descriptor _cache_)
083c: 6 CS cache (CS descriptor _cache_)
0842: 6 SS cache (SS descriptor _cache_)
0848: 6 DS cache (DS descriptor _cache_)
084e: 6 GDTR (Global Descriptor Table)
0854: 6 LDT cache (Local Descriptor_cache_)
085a: 6 IDTR (Interrupt Descriptor table)
0860: 6 TSS cache (Task State Segment _cache_)
Descriptor caches layout:
3 bytes 24 bit physical address of segment
1 byte access rights byte, same format as access right byte
in a regular descriptor. The 'present' bit now
represents a 'valid' bit. If this bit is cleared
(zero) the segment is invalid and accessing it will
trigger exception 0dh.
The DPL (Descriptor Privilege Level) fields of the CS
and SS descriptor caches determine the CPL
(Current Privilege Level).
2 bytes 16 bit segment length limit.
This layout is the same for the GDTR and IDTR registers,
except that the access rights byte must be zero.
The register caches are internal CPU registers containing a copy of the last
in protected mode (e.g. ES). An outline of the basics of 286 protected
mode register caching and register layout is beyond the scope of this file
The 386 LOADALL loads 204 (dec) bytes from the address at ES:EDI and resumes
execution in the specified state.
Memory description for LOADALL read area on 386+:
(addresses are in hexadecimal, lengths in decimal)
relative offset: Bytes: Registers:
0000: 4 CR0
0004: 4 EFLAGS
0008: 4 EIP
000c: 4 EDI
0010: 4 ESI
0014: 4 EBP
0018: 4 ESP
001c: 4 EBX
0020: 4 EDX
0024: 4 ECX
0028: 4 EAX
002c: 4 DR6
0030: 4 DR7
0034: 4 TR
0038: 4 LDT
003c: 4 GS (zero extended)
0040: 4 FS (zero extended)
0044: 4 DS (zero extended)
0048: 4 SS (zero extended)
004c: 4 CS (zero extended)
0050: 4 ES (zero extended)
0054: 12 TSS descriptor cache
0060: 12 IDT descriptor cache
006c: 12 GDT descriptor cache
0078: 12 LDT descriptor cache
0084: 12 GS descriptor cache
0090: 12 FS descriptor cache
009c: 12 DS descriptor cache
00a8: 12 SS descriptor cache
00b4: 12 CS descriptor cache
00c0: 12 ES descriptor cache
Descriptor caches layout:
1 byte zero
1 byte access rights byte, same as 286
2 bytes zero
4 bytes 32 bit physical base address of segment
4 bytes 32 bit segment length limit
LSL Load Segment Limit
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