Output: after CPUID:
EAX = RRRR RFMS : revision information
R = Reserved Zero, but reserved
F = Family (4=486, 5=Pentium)
M = Model (3 on tested 486DX-2/66, 1 on tested Pentium/60)
S = Stepping (5 on tested 486DX-2/66, 3 on tested Pentium/60)
EBX = RRRR RRRR
R = Reserved Zero, but reserved
ECX = RRRR RRRR
R = Reserved Zero, but reserved
EDX = xxxx xxxx : Bitmapped features, 1 means option available
Bit 0 = FPU built-in (supported on 486 and Pentium)
Bit 1 = V-86 mode extensions present
Bit 2 = I/O breakpoints possible
Bit 3 = 4 MB paging supported
Bit 4 = Time Stamp Counter present
Bit 5 = Has Pentium compatible Model Specific Registers
Bit 6 = Reserved (0)
Bit 7 = Machine Check Exception supported (P5 only)
Bit 8 = CMPXCHG8B supported (apparently Pentium only)
Bits 9-31 Reserved
Assume zero if bit is not mentioned.
Note that this instruction is not supported on all 486 CPUs. However,
Christian Ludloff has tested it on some 486 DX and 486 SX models, in
addition to the Pentium/60 and found them to be present on those machines.
Any step and model information you find this instruction to run on is
welcomed. Please forward it to Christian.
Apparently all new(er) Intel CPUs are equipped with (some) of these
extensions, not just the Pentium.
CR0-4 register layout (386+)
──────────────────────────────────────────────────────────────────────────────
= CR0: Some bits remain from the Machine Status Word of the 286.
Bit 31 16 0
┌─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬┴┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┐
│P│C│N│r│r│r│r│r│r│r│r│r│r│A│r│W│r│r│r│r│r│r│r│r│r│r│n│e│t│E│m│p│
└┼┴┼┴┼┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴┼┴─┴┼┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴┼┴┼┴┼┴┼┴┼┴┼┛
│┌┛ │ │ └───────────────────┐ │ │ │ │ │ │
││┌─┛ └─────────────────────┐ │ │ │ │ │ │ │
││└NW Not Write through (1 if write through) │ │ │ │ │ │ │ │
│└─CD Cache Disable (1 if disabled) │ │ │ │ │ │ │ │
└──PE Paging Enabled │ │ │ │ │ │ │ │
AC Alignment mask (1=masked)─────────────────┛ │ │ │ │ │ │ │
WP Write Protect (1 if read-only pages protected)│ │ │ │ │ │
NE Numeric Error (1 if errors should be ignored)─┛ │ │ │ │ │
ET Extension Type (1=387 type FPU,0=287 type FPU)──┛ │ │ │ │
TS Task Switch (1=task switch has occurred)──────────┛ │ │ │
EP Emulate Processor Extension ────────────────────────┛ │ │
(1=execute exception 7 on FPU codes) │ │
MP Math Present (1=_FPU_ will handle FPU codes)──────────┛ │
PE Protection Enabled (1=Protected mode activated)─────────┛
If EP=1 and MP=0, the FPU codes will be handled by software routines
via exception 7. Coprocessor emulators use this property.
= CR1: Is reserved
= CR2: Linear 32-bit address of Page Fault
= CR3: Page Directory Base Register (386+)
Bit 31 16 0
┌─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬┴┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┐
│x│x│x│x│x│x│x│x│x│x│x│x│x│x│x│x│x│x│x│x│r│r│r│r│r│r│r│p│P│r│r│r│
└┼┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴┼┴─┴─┴─┴─┴─┴─┴─┴┼┴┼┴─┴─┴─┛
└─────Page Directory Base Register────┛ │ │ PDBR
(used in the Paging process implemented on the 386+) │ │
│ │
Page-level Cache Disable (486+)───────────────────────┛ │ PCD
Page-level Writes Transparent (486+)────────────────────┛ PWT
= CR4: Extended Machine Control (Pentium+)
Bit 31 16 0
┌─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬┴┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┐
│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│r│M│r│p│D│T│P│V│
└─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴┼┴─┴┼┴┼┴┼┴┼┴┼┛
Machine Check Enable (1=enabled)──────────────────┛ │ │ │ │ │ MCE
Page Size Extension (1=4 Mb paging instead of 4 Kb)───┛ │ │ │ │ PSE
Debugging Extension (1=breakpoints also valid for I/O)──┛ │ │ │ DE
Time Stamp instruction Disable (1=RDTSC only with CPL=0)──┛ │ │ TSD
Protected mode Virtual Interrupts (1=use VI flag in PM)─────┛ │ PVI
Virtual86 mode Virtual Interrupts (1=use VI flag in VM)───────┛ VME
The VME bit allows a V86 (or VM) task to use the 'virtual' interrupt
flag. Setting and clearing the interrupt flag (IF) in EFLAGS is no
longer intercepted by the V86 Monitor program (a very time consuming
procedure), instead, the Pentium+ sets and clears the VI flag in
EFLAGS, instead of the IF flag. This saves task switches to the
monitor to handle the CLI and STI instructions and thus a lot
of time in general purpose 8086 programs running in V86 mode.
The PVI bit allows the same for Protected Mode procedures who would
otherwise need supervision by a different task. That is:
Tasks with CPL<0 may now call tasks with CPL=0 without crashing
the system, but only under specific circumstances.
The TSD bit changes the CPL-sensitivity of the RDTSC (Read Time
Stamp Counter) instruction, a built-in CPU counter which is
incremented every internal clockpulse.
When TSD is 0, <RDTSC> is accessible for all CPL levels.
With TSD set to 1 however, RDTSC is available only to tasks with
CPL=0.
The DE bit allows the Pentium+ to set breakpoints in I/O space
using the breakpoint registers. The R/W coding 10b is used to
indicate that the breakpoint is in I/O space on the Pentium+.
The 10b encoding was marked as 'invalid' for pre-Pentium CPUs.
The PSE bit determines the size of the pages controlled by the
Paging Unit. With PSE = 0, the Paging mechanism uses 4 Kb pages.
With PSE set to 1 however, the Paging mechanism uses 4 Mb pages.
The MCE bit is used to allow generation of a Machine Check Exception.
This exception is the result of a Parity error _within_ the Pentium
or an active BUSCHK signal (low) on pin T3 (upper right hand corner,
fourth pin from right, third from top when pin A1 is upper left
corner, TOP view). The exception is vectored through interrupt 18d
(or 12h). Execution after this exception may void system integrity.
The Machine Check Address register holds the value of the address
bus at the moment the event took place.
The Machine Check Type register holds the type of bus access at the
time the event took place.
Both these registers are internal 64 bit registers which can only be
read through the instruction <RDMSR> (Read Model Specific Register).
See also <WRMSR> (Write Model Specific Register).
EFLAGS register layout (8088 to Pentium & NEC)
──────────────────────────────────────────────────────────────────────────────
Bit 31 16 0
┌─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬┴┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┼─┬─┬─┬─┐
│r│r│r│r│r│r│r│r│r│r│c│p│v│a│V│R│M│N│IOP│O│D│I│T│S│Z│r│A│r│P│r│C│
└─┴─┴─┴─┴─┴─┴─┴─┴─┴─┴┼┴┼┴┼┴┼┴┼┴┼┴┼┴┼┴┼┴─┴┼┴┼┴┼┴┼┴┼┴┼┴─┴┼┴─┴┼┴─┴┼┛
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │Carry
CPUID available ─────┛ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ Parity
Virtual Interrupt Pending│ │ │ │ │ │ │ │ │ │ │ │ │ └Aux carry
Virtual Interrupt flag ──┛ │ │ │ │ │ │ │ │ │ │ │ └──────── Zero
Alignment check ───────────┛ │ │ │ │ │ │ │ │ │ └────────── Sign
Virtual-86 mode enabled ─────┛ │ │ │ │ │ │ │ └ Trap (step mode)
Resume flag ───────────────────┛ │ │ │ │ │ └── Interrupt enable
Mode Flag ───────────────────────┛ │ │ │ └──── Direction (1=up)
Nested Task ───────────────────────┛ │ └────────────── Overflow
└── I/O privilege level 0..3