Function:

Basically copies bit(op2) from op1 into CY and sets bit(op2) of op1 to 1.
Memory variant is more complex. Do not use on memory mapped I/O ports or
memory operands that span into or lie completely within nonexistent memory.
In the case of memory mapped I/O ports, use MOV and TEST instead.




Chip Step information for Intel CPUs
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CPUs are manufactured in models (like the 80386). While these models are
manufactured, errors in the mask layout and mask design may become
apparent. These errors may be corrected before a new batch of chips is
made. To distinguish between these revisions an identification code is
placed within the mask design on 386+ CPUs. By testing the CPU with CPUID
or by performing a RESET, this information is copied to specific registers.

The register used to hold mask info after a RESET is DX (apparently also
sometimes the high word of EDX on some 486s).

This page lists some component and revision ID's found in the DX register
for the 386SX, 386DX, 486SX and 486DX models from Intel.


        CPU:        DX:     Step:
        386SX       2304h   A0
                    2305h   B
                    2306h   C
                    2308h   D1

        386DX       0303h   B0 - B10
                    0305h   D0
                    0308h   D1 & D2

        486SX       0420h   A0

        486DX       0000h   A1
                    0401h   Bn
                    0302h   C0
                    0404h   D0
                    0410h   cAn
                    0411h   cBn




CLEAR1  Clears a specific bit to 0 (NEC V20/30 only)
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