Format of PCI IRQ Routing Table slot entry
Offset Size Description (Table M086)
00h BYTE PCI bus number
01h BYTE PCI device number (bits 7-3)
02h BYTE link value for INTA#
03h WORD IRQ bitmap for INTA#
05h BYTE link value for INTB#
06h WORD IRQ bitmap for INTB#
08h BYTE link value for INTC#
09h WORD IRQ bitmap for INTC#
0Bh BYTE link value for INTD#
0Ch WORD IRQ bitmap for INTD#
0Eh BYTE slot number (00h = motherboard, other = vendor-specific)
0Fh BYTE reserved
See Also: #M085,#0956 at INT 1A/AX=B406h
--------H-mFEC00000--------------------------
MEM FEC00000h - Pentium - 82379AB I/O APIC - I/O REGISTER SELECT
Size: DWORD
Desc: bits 7-0 of the I/O Register Select memory location specify which
of the APIC's registers appears in the I/O Window at FExxx010h
Range: the Multiprocessor Specification calls for I/O APICs to be memory-
mapped on 4K boundaries between FEC00000h and FEDFC000h; the Intel
82379AB I/O APIC can be memory-mapped on any 1K boundary within
FEC0000h-FEC0F800h
Note: this memory-mapped register is also supported by the Intel 82093AA
I/O APIC
See Also: MEM FEC00010h,MEM FEE00000h,MEM xxxxh:xxx0h"Multiprocessor"
--------H-mFEC00010--------------------------
MEM FEC00010h - Pentium - 82379AB I/O APIC - I/O WINDOW
Size: DWORD
Range: the Multiprocessor Specification calls for I/O APICs to be memory-
mapped on 4K boundaries between FEC00000h and FEDFC000h
Note: this memory-mapped register is also supported by the Intel 82093AA
I/O APIC
See Also: MEM FEC00010h
(Table M087)
Values for Intel 82379AB/82093AA I/O APIC registers:
00h APIC ID
01h APIC version (read-only)
bits 31-24: reserved
bits 23-16: maximum redirection entry
bits 15-8: reserved
bits 7-0: APIC version (11h for 82093AA)
02h APIC arbitration ID (read-only)
bits 31-28: reserved
bits 27-24: arbitration ID
bits 23-0: reserved
10h-11h redirection table entry 0 (10h=low DWORD, 11h=high DWORD)
12h-13h redirection table entry 1 (see !!!)
...
2Eh-2Fh redirection table entry 15
---82093AA only---
30h-31h redirection table entry 16
...
3Eh-3Fh redirection table entry 23
Bitfields for APIC redirection table entry:
Bit(s) Description (Table M088)
63-56 destination
!!!29056601.pdf pg. 10
55-17 reserved
16 interrupt mask
15 trigger mode
14 remote IRR (read-only)
13 interrupt input pin polarity
12 delivery status (read-only)
11 destination mode
10-8 delivery mode
7-0 interrupt vector (10h-FEh)
--------H-mFEE00000--------------------------
MEM FEE00000h - Pentium - LOCAL APIC
Size: 4096 BYTEs
Notes: the Advanced Programmable Interrupt Controller built into
multiprocessor-capable Pentiums (P54C, etc. -- basically 75MHz and
faster Pentiums) maps its registers into the top of the physical
address space on data reads and writes, but not on code reads;
data accesses to the APIC registers do not cause external bus
cycles
the APIC's registers are only visible when the APIC is enabled (which
occurs at CPU reset when external data lines contain proper signals);
all accesses to APIC registers should use 32-bit reads or writes, as
8-bit and 16-bit accesses may produce unpredictable results
the PentiumPro (P6) permits the address at which the local APIC
appears to be changed with Model-Specific Register 0000001Bh
See Also: MEM FEC00000h,MEM FEE00020h,MEM xxxxh:xxx0h"Multiprocessor"
See Also: MSR 0000001Bh
--------H-mFEE00020--------------------------
MEM FEE00020h - Pentium - LOCAL APIC - LOCAL APIC ID REGISTER
Size: DWORD
See Also: MEM FEE00030h
--------H-mFEE00030--------------------------
MEM FEE00030h - Pentium - LOCAL APIC - LOCAL APIC VERSION REGISTER
Size: DWORD
Note: read-only
See Also: MEM FEE00020h
--------H-mFEE00040--------------------------
MEM FEE00040h - Pentium - LOCAL APIC - RESERVED
See Also: MEM FEE00000h
--------H-mFEE00050--------------------------
MEM FEE00050h - Pentium - LOCAL APIC - RESERVED
See Also: MEM FEE00000h
--------H-mFEE00060--------------------------
MEM FEE00060h - Pentium - LOCAL APIC - RESERVED
See Also: MEM FEE00000h
--------H-mFEE00070--------------------------
MEM FEE00070h - Pentium - LOCAL APIC - RESERVED
See Also: MEM FEE00000h
--------H-mFEE00080--------------------------
MEM FEE00080h - Pentium - LOCAL APIC - TASK PRIORITY REGISTER (TPR)
Size: DWORD
--------H-mFEE00090--------------------------
MEM FEE00090h - Pentium - LOCAL APIC - ARBITRATION PRIORITY REGISTER (APR)
Size: DWORD
Note: read-only
--------H-mFEE000A0--------------------------
MEM FEE000A0h - Pentium - LOCAL APIC - END OF INTERRUPT REGISTER (EOI)
Size: DWORD
Note: write-only
--------H-mFEE000A0--------------------------
MEM FEE000A0h - Pentium - LOCAL APIC - PROCESSOR PRIORITY REGISTER (PPR)
Size: DWORD
Note: read-only
See Also: MEM FEE00000h
--------H-mFEE000B0--------------------------
MEM FEE000B0h - Pentium - LOCAL APIC - RESERVED
See Also: MEM FEE00000h
--------H-mFEE000C0--------------------------
MEM FEE000C0h - Pentium - LOCAL APIC - REMOTE READ REGISTER
Size: DWORD
Note: read-only
--------H-mFEE000D0--------------------------
MEM FEE000D0h - Pentium - LOCAL APIC - LOGICAL DURATION REGISTER (LDR)
Size: DWORD
See Also: MEM FEE00000h
--------H-mFEE000E0--------------------------
MEM FEE000E0h - Pentium - LOCAL APIC - DESTINATION FORMAT REGISTER (DFR)
Size: DWORD
bits 27-0: read-only
bits 31-28: read-write
--------H-mFEE000F0--------------------------
MEM FEE000F0h - Pentium - LOCAL APIC - SPURIOUS INTERRUPT VECTOR REGISTER
Size: DWORD
bits 3-0, read-only
bits 9-4, read/write
--------H-mFEE00100--------------------------
MEM FEE00100h - Pentium - LOCAL APIC - IN-SERVICE REGISTER (ISR)
Size: 128 BYTEs
Note: read-only
See Also: MEM FEE00200h
--------H-mFEE00180--------------------------
MEM FEE00180h - Pentium - LOCAL APIC - TRIGGER MODE REGISTER (TMR)
Size: 128 BYTEs
Note: read-only
See Also: MEM FEE00000h
--------H-mFEE00200--------------------------
MEM FEE00200h - Pentium - LOCAL APIC - INTERRUPT REQUEST REGISTER (IRR)
Size: 128 BYTEs
Note: read-only
See Also: MEM FEE00100h
--------H-mFEE00280--------------------------
MEM FEE00280h - Pentium - LOCAL APIC - ERROR STATUS REGISTER
Size: DWORD
Note: read-only
Bitfields for Pentium APIC error status register:
Bit(s) Description (Table M089)
0 send checksum error
1 receive checksum error
2 send accept error
3 receive accept error
4 reserved
5 send illegal vector
6 receive illegal vector
7 illegal register address
31-8 reserved
--------H-mFEE00300--------------------------
MEM FEE00300h - Pentium - LOCAL APIC - INTERRUPT COMMAND REGISTER (ICR)
Size: DWORD
Note: this is the low half of the 64-bit ICR
See Also: MEM FEE00310h,#M090
Bitfields for Pentium APIC Interrupt Command Register:
Bit(s) Description (Table M090)
7-0 interrupt vector number
10-8 delivery mode (see #M091)
11 destination mode
12 delivery status (read-only)
1 = transfer pending
13 reserved
14 level (0 = INIT Level Deassert message, 1 = anything else)
15 trigger mode (1)
17-16 remote read status (read-only)
19-18 destination shorthand
00 as specified by destination field
01 self
10 all including self
11 all except self
55-20 reserved
63-56 destination for interrupt request or message
See Also: #M093