Format of Multiprocessor Specification configuration table entries

Offset  Size    Description     (Table M082)
 00h   BYTE    entry type code
       00h processor
       01h bus
       02h I/O APIC
       03h I/IO interrupt assignment
       04h local interrupt assignment
       80h system address space mapping
       81h bus hierarchy descriptor
       82h compatibility bus address space modifier
---processor---
 01h   BYTE    local APIC identifier
 02h   BYTE    local APIC version
 03h   BYTE    CPU flags
       bit 0: processor usable
       bit 1: bootstrap processor
 04h   WORD    CPU type
       bits 11-8: CPU family
       bits 7-4: CPU model
       bits 3-0: stepping
       (bits 11-0 all set indicate non-Intel-compatible CPU)
 06h  2 BYTEs  unused
 08h   DWORD   feature flags (as returned by Pentium CPUID instruction)
 0Ch  8 BYTEs  reserved
---bus---
 01h   BYTE    bus ID (assigned sequentially from 00h by BIOS)
 02h  6 BYTEs  bus type (blank-padded ASCII string) (see #M083)
---I/O APIC---
 01h   BYTE    APIC identifier
 02h   BYTE    APIC version
 03h   BYTE    I/O APIC flags
       bit 0: enabled
       bits 7-1: reserved
 04h   DWORD   base address for APIC
---I/O,local interrupt assignment---
 01h   BYTE    interrupt type
       00h vectored interrupt (from APIC)
       01h NMI
       02h system management interrupt
       03h vectored interrupt (from external PIC)
 02h   BYTE    APIC control (see #M084)
 03h   BYTE    unused
 04h   BYTE    source bus identifier
 05h   BYTE    source bus IRQ
 06h   BYTE    destination I/O APIC identifier
 07h   BYTE    destination I/O APIC interrupt pin number
---system address space mapping---
 01h   BYTE    entry length (14h)
 02h   BYTE    bus ID
 03h   BYTE    address type (00h I/O, 01h memory, 02h prefetch)
 04h   QWORD   starting address of region visible to bus
 0Ch   QWORD   length of region visible to bus
---bus hierarchy descriptor---
 01h   BYTE    entry length (08h)
 02h   BYTE    bus ID
 03h   BYTE    bus information
       bit 0: subtractive decoding
 04h   BYTE    ID of parent bus
 05h  3 BYTEs  reserved
---compatibility bus address space modifier---
 01h   BYTE    entry length (08h)
 02h   BYTE    bus ID
 03h   BYTE    address modifier
       bit 0: remove address ranges in predefined range list from
             bus's address space
 04h   DWORD   number indicating predefined address space range to be removed
       00h ISA-compatible I/O range (x100h-x3FFh and aliases)
       01h VGA-compatible I/O range (x3B0h-x3BBh,x3C0h-x3DFh,aliases)

See Also: #M081
(Table M083)
Values for Multiprocessor Specification bus name:
 "CBUS"        Corollary CBus
 "CBUSII"  Corollary CBus II
 "EISA"
 "FUTURE"  IEEE FutureBus
 "INTERN"  internal bus
 "ISA"
 "MBI"     Multibus I
 "MBII"        Multibus II
 "MCA"     Microchannel
 "MPI"
 "MPSA"
 "NUBUS"   Apple Macintosh NuBus
 "PCI"
 "PCMCIA"
 "TC"      DEC TurboChannel
 "VL"      VESA Local Bus
 "VME"     VMEbus
 "XPRESS"  Express System Bus

See Also: #M082
Bitfields for Multiprocessor Specification APIC control:
Bit(s) Description (Table M084)
 1-0   input signal polarity
   00 conforms to bus specification
   01 active high
   10 reserved
   11 active low
 3-2   trigger mode
   00 conforms to bus specification
   01 edge-triggered
   10 reserved
   11 level-triggered

See Also: #M082
--------X-Mxxxxxxx0--------------------------
MEM xxxxh:xxx0h - PCI IRQ Routing Table Specification v1.0
Size:  N paragraphs (N >= 2)
Range: any paragraph boundary within the range F0000h to FFFFFh
InstallCheck: scan for the signature string "$PIR" followed by a valid
     PCI IRQ Routing Table