Format of ACPI Fixed ACPI Description Table

Offset  Size    Description     (Table M072)
 00h 28 BYTEs  System Description Table Header (see #M070)
       signature "FACP"
 1Ch   DWORD   physical address of the Firmware ACPI Control Structure
         (see #M076)
 20h   DWORD   physical address of the Differentiated System Description Table
         (see #M074)
 24h   BYTE    interrupt mode
       00h dual PIC (industry-standard AT-type)
       01h multiple APIC (see #M075)
 25h   BYTE    reserved
 26h   WORD    system vector of SCI interrupt
 28h   DWORD   I/O port address of SMI command port
 2Ch   BYTE    value to write to SMI comamnd port to disable SMI ownership
         of ACPI hardware registers
 2Dh   BYTE    value to write to SMI comamnd port to re-enable SMI ownership
         of ACPI hardware registers
 2Eh  2 BYTEs  reserved
 30h   DWORD   I/O port address of Power Management 1a Event Register Block
 34h   DWORD   I/O port address of Power Management 1b Event Register Block
       (optional, 00000000h if not supported)
 38h   DWORD   I/O port address of Power Management 1a Control Register Block
 3Ch   DWORD   I/O port address of Power Management 1b Control Register Block
       (optional, 00000000h if not supported)
 40h   DWORD   I/O port address of Power Management 2 Control Register Block
       (optional, 00000000h if not supported)
 44h   DWORD   I/O port address of Power Management Timer Control Reg. Block
 48h   DWORD   I/O port address of Generic Purpose Event 0 Register Block
       (optional, 00000000h if not supported)
 4Ch   DWORD   I/O port address of Generic Purpose Event 1 Register Block
       (optional, 00000000h if not supported)
 50h   BYTE    size of Power Management 1a/1b Event Register Block (>= 4)
 51h   BYTE    size of Power Management 1a/1b Control Register Block (>= 1)
 52h   BYTE    size of Power Management 2 Control Register Block (>= 1)
 53h   BYTE    size of Power Management Timer Control Register Block (>= 1)
 54h   BYTE    size of Generic Purpose Event 0 Register Block (multiple of 2)
 55h   BYTE    size of Generic Purpose Event 1 Register Block (multiple of 2)
 56h   BYTE    offset within General Purpose Event model for GPE1-based events
 57h   BYTE    reserved
 58h   WORD    worst-case hardware latency (microseconds) for entering/leaving
         state C2; >100 if C2 not supported
 5Ah   WORD    worst-case hardware latency (microseconds) for entering/leaving
         state C3; >100 if C3 not supported
 5Ch   WORD    size of contiguous cacheable memory which must be read to flush
         all dirty lines from a processor's memory cache; use if
         fixed feature flag WBINVD (see #M073) is clear
       0000h if flushing not supported
 5Eh   WORD    memory stride size (in bytes) to flush processor's memory cache
 60h   BYTE    index of processor's duty cycle setting within
         processor's P_CNT register
 61h   BYTE    size of processor's duty cycle setting in bits
 62h   BYTE    index within RTC CMOS RAM of the day-of-month alarm value
       00h = not supported
 63h   BYTE    index within RTC CMOS RAM of the month-of-year alarm value
       00h = not supported
 64h   BYTE    index within RTC CMOS RAM of the century alarm value
       00h = not supported
 65h   BYTE    reserved
 66h   DWORD   fixed feature flags (see #M073)

See Also: #M069
Bitfields for ACPI Fixed Feature Flags:
Bit(s) Description (Table M073)
 0 WBINVD instruction is currectly supported by processor
 1 WBINVD instruction flushes all caches and maintains coherency, but
     does not guarantee invalidation of all caches
 2 all processors support C1 sleep state
 3 C2 sleep state is configured to work on multiprocessor system
 4 power button is handled as a generic feature
 5 RTC wake-up state is not supported in fixed register space
 6 TMR_VAL size
   =0 24 bits
   =1 32 bits
 7-31  reserved

See Also: #M072