Port 3CF, 05  -  Graphics Mode Register

        1xxx xxxx  Reserved
        x1xx xxxx  256-Color Mode
                     When set to 0, this bit allows bit 5 to control the
                     loading of the shift registers. When set to 1, this
                     bit causes the shift registers to be loadet in a
                     manner that supports the 256-color mode.
        xx1x xxxx  Shift Register Mode
                     When set to 1, this bit directs the shift registers
                     in the graphics controller to format the serial data
                     stream with even-numbered bits from both maps on
                     even-numbered maps, and odd-numbered bits from both
                     mamps on the odd-numbered maps. This bit is used for
                     modes 4 and 5.
        xxx1 xxxx  Odd/Even
                     When set to 1, this bit selects the odd/even
                     addressing mode used by the IBM Color/Graphics
                     Adapter. Normally, the value here follows the value
                     of Memory Mode (3C5, 04) register bit 2 in the
                     sequencer.
        xxxx 1xxx  Read Mode
                     When this bit is set to 1, the system reads the results
                     of the comparation of the four memory maps and the
                     Color Compare Register (3CF, 02).
                     When this bit is set to 0, the system reads data from
                     the memory map selected by the Read Map Select
                     (3CF, 04) Register, or by the two low-order bits of
                     the memory address (this selection depends on the
                     chain-4 bit in the Memory Mode Register (3C5, 04) in
                     the sequencer).
        xxxx x1xx  Reserved
        xxxx xx11  Write Mode
                     The write mode selected and its operation are defined
                     in the table below. The logic operation specified by
                     the function select bits is performed on system data
                     for modes 0, 2 and 3.


        Write Mode
        Bits
        1 0   Mode Description                                            
        0 0   Each memory map is written with the system data rotated by
              the count in Data Rotate register. If the set/reset function
              is enabled for a specific map, that map receives the 8-bit
              value contained in the Set/Reset register.
        0 1   Each memory map is written with the contens of the system
              latches. These latches are loadedby a system read operation.
        1 0   Memory map n is written with the 8-bit value of the value
              of the data bit n.
        1 1   Each memory map is written with the 8-bit value contained
              in the Set/Reset register for that map (the Enable Set/Reset
              register has no effect). Rotated system data is ANDed with
              the Bit Mask register to form an 8-bit value that performs
              the same function as the Bit Mask register in write modes
              0 and 2 (see also Bit Mask register - 3CF, 08).