Port 3C5, 01  -  Clocking Mode Register

                11xx xxxx  Reserved
                xx1x xxxx  Screen Off
                             When set to 1, this bit turns off the display
                             and assigns maximum memory bandwidth to the
                             system. Although the display is blanked, the
                             synchronization pulses are maintained. This
                             bit can be used for rapid full-screen updates.
                xxx1 xxxx  Shift 4
                             When this bit and bit 2 are set to 0, the
                             video serializers are loadet every character
                             clock. When this bit is set to 1, the seria-
                             lizers are loadet every fourth character
                             clock, which is usefull when 32 bits are
                             fetched per cycle and chained together is the
                             shift registers.
                xxxx 1xxx  Dot Clock
                             When set to 0, this bit selects the normal
                             dot clocks derived from the master clock
                             input. When this bit is set to 1, the master
                             clock will be divided by 2 to generate the dot
                             clock. All other timings are affected because
                             they are derived from the dot clock. The dot
                             clock divided by 2 is used for 320 and 360
                             PEL modes.
                xxxx x1xx  Shift Load
                             When this bit and bit 4 are set to 0, the video
                             serializers are loaded every character clock.
                             When this bit is to 1, the video serializers are
                             loaded every other character clock, which is
                             usefull when 16 bits are fetched per cycle
                             and chained together in the shift registers.
                xxxx xx1x  Reserved
                xxxx xxx1  8/9 dot clocks
                             When set to 0, this bit directs the sequencer
                             to generate character clocks 9 dots wide; when
                             set to 1, it directs the sequencer to generate
                             character clocks 8 dots wide. The 9 dot mode
                             is for alphanumeric modes 0+, 1+, 2+, 3+, 7
                             and 7+ only; the 9th dot equals the 8th dot for
                             ASCII codes C0h through DFh. All other modes
                             must use 9 dots per character clock.